Lines Matching defs:v4l2_ctrl_hevc_sps
2171 struct v4l2_ctrl_hevc_sps { struct
2172 __u8 video_parameter_set_id;
2173 __u8 seq_parameter_set_id;
2174 __u16 pic_width_in_luma_samples;
2175 __u16 pic_height_in_luma_samples;
2176 __u8 bit_depth_luma_minus8;
2177 __u8 bit_depth_chroma_minus8;
2178 __u8 log2_max_pic_order_cnt_lsb_minus4;
2179 __u8 sps_max_dec_pic_buffering_minus1;
2180 __u8 sps_max_num_reorder_pics;
2181 __u8 sps_max_latency_increase_plus1;
2182 __u8 log2_min_luma_coding_block_size_minus3;
2183 __u8 log2_diff_max_min_luma_coding_block_size;
2184 __u8 log2_min_luma_transform_block_size_minus2;
2185 __u8 log2_diff_max_min_luma_transform_block_size;
2186 __u8 max_transform_hierarchy_depth_inter;
2187 __u8 max_transform_hierarchy_depth_intra;
2188 __u8 pcm_sample_bit_depth_luma_minus1;
2189 __u8 pcm_sample_bit_depth_chroma_minus1;
2190 __u8 log2_min_pcm_luma_coding_block_size_minus3;
2191 __u8 log2_diff_max_min_pcm_luma_coding_block_size;
2192 __u8 num_short_term_ref_pic_sets;
2193 __u8 num_long_term_ref_pics_sps;
2194 __u8 chroma_format_idc;
2195 __u8 sps_max_sub_layers_minus1;
2197 __u8 reserved[6];
2198 __u64 flags;