Lines Matching +full:flow +full:- +full:level
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
175 #define UART_EFR_CTS 0x80 /* CTS flow control */
176 #define UART_EFR_RTS 0x40 /* RTS flow control */
180 * the low four bits control software flow control
195 #define UART_TI752_TLR 7 /* I/O: trigger level register */
217 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
239 * The Intel XScale on-chip UARTs define these bits
257 #define UART_RFL 0x03 /* Receiver FIFO level */
258 #define UART_TFL 0x04 /* Transmitter FIFO level */
266 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
267 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
268 #define UART_FCL 0x06 /* Flow Control Level Lower */
269 #define UART_FCH 0x07 /* Flow Control Level Higher */
275 #define UART_NMR 0x0D /* Nine-bit Mode Register */
283 #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
291 * These definitions are for the RSA-DV II/S card, from
293 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
296 #define UART_RSA_BASE (-8)
302 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
303 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
343 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
363 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
364 #define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */
371 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */