Lines Matching +full:enable +full:- +full:modem +full:- +full:interrupt
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
24 #define UART_IER 1 /* Out: Interrupt Enable Register */
25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
34 #define UART_IIR 2 /* In: Interrupt ID Register */
36 #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
37 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
39 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
40 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
44 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
55 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
114 #define UART_LCR_PARITY 0x08 /* Parity Enable */
128 #define UART_MCR 4 /* Out: Modem Control Register */
131 #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
133 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
143 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
150 #define UART_MSR 6 /* In: Modem Status Register */
222 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
239 * The Intel XScale on-chip UARTs define these bits
241 #define UART_IER_DMAE 0x80 /* DMA Requests Enable */
242 #define UART_IER_UUE 0x40 /* UART Unit Enable */
243 #define UART_IER_NRZE 0x20 /* NRZ coding Enable */
244 #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
266 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
267 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
275 #define UART_NMR 0x0D /* Nine-bit Mode Register */
284 #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
285 #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
286 #define UART_ACR_ASREN 0x80 /* Additional status enable */
291 * These definitions are for the RSA-DV II/S card, from
293 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
296 #define UART_RSA_BASE (-8)
301 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
302 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
305 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
307 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
308 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
309 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
310 #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
311 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
322 #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
343 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
344 #define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
345 #define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
363 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
371 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
383 #define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */