Lines Matching +full:auto +full:- +full:flow +full:- +full:control
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
54 #define UART_FCR 2 /* Out: FIFO Control Register */
105 #define UART_LCR 3 /* Out: Line Control Register */
111 #define UART_LCR_SBC 0x40 /* Set break control */
128 #define UART_MCR 4 /* Out: Modem Control Register */
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
175 #define UART_EFR_CTS 0x80 /* CTS flow control */
176 #define UART_EFR_RTS 0x40 /* RTS flow control */
178 #define UART_EFR_ECB 0x10 /* Enhanced control bit */
180 * the low four bits control software flow control
194 #define UART_TI752_TCR 6 /* I/O: transmission control register */
216 #define UART_FCTR 1 /* Feature Control Register */
217 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
239 * The Intel XScale on-chip UARTs define these bits
259 #define UART_ICR 0x05 /* Index Control Register */
262 #define UART_ACR 0x00 /* Additional Control Register */
268 #define UART_FCL 0x06 /* Flow Control Level Lower */
269 #define UART_FCH 0x07 /* Flow Control Level Higher */
275 #define UART_NMR 0x0D /* Nine-bit Mode Register */
279 * The 16C950 Additional Control Register
283 #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
291 * These definitions are for the RSA-DV II/S card, from
293 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
296 #define UART_RSA_BASE (-8)
302 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
328 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
343 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
356 #define UART_OMAP_SCR 0x10 /* Supplementary control register */
363 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
371 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */