Lines Matching +full:ats +full:- +full:supported
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <[email protected]>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
160 /* 0x3c-0x3d are same as for htype 0 */
191 /* 0x3c-0x3d are same as for htype 0 */
199 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
205 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
206 /* 0x48-0x7f reserved */
217 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
219 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
222 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
224 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
227 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
246 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
247 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
256 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
272 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
273 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
274 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
275 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
276 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
277 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
278 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
283 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
295 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
311 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
312 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
316 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */
317 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */
318 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */
319 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */
320 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */
321 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */
323 /* MSI-X registers (in MSI-X capability) */
327 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
337 /* MSI-X Table entry format (in memory mapped by a BAR) */
354 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
355 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
383 /* 0-5 map to BARs 0-5 respectively */
389 /* 9-14 map to VF BARs 0-5 respectively */
392 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
395 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
399 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
400 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
403 /* 0x08-0xfc reserved */
412 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
415 /* PCI-X registers (Type 0 (non-bridge) devices) */
436 #define PCI_X_STATUS 4 /* PCI-X capabilities */
439 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
455 /* PCI-X registers (Type 1 (bridge) devices) */
461 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
483 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
484 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
498 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
504 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
529 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
536 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Max Link Speed (prior to PCIe r3.0: Supported Link Speeds…
593 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
594 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
606 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
622 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
635 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
656 #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */
657 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
666 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
667 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
668 #define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefixes */
672 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
684 #define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
685 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
686 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
687 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
688 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
689 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
690 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */
691 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
694 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
695 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
696 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
697 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
698 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
699 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
707 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
711 /* Extended Capabilities (PCI-X 2.0 and Express) */
723 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
726 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
727 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
746 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
786 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
801 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
809 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
867 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
868 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
907 /* Alternative Routing-ID Interpretation */
919 #define PCI_ATS_CAP 0x04 /* ATS Capability Register */
923 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
924 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
938 #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
944 #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */
945 #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */
954 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
957 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
963 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
972 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
990 #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
1009 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
1016 #define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */
1026 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1036 #define PCI_TPH_CAP_ST_NS 0x00000001 /* No ST Mode Supported */
1037 #define PCI_TPH_CAP_ST_IV 0x00000002 /* Interrupt Vector Mode Supported */
1038 #define PCI_TPH_CAP_ST_DS 0x00000004 /* Device Specific Mode Supported */
1039 #define PCI_TPH_CAP_EXT_TPH 0x00000100 /* Ext TPH Requester Supported */
1043 #define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */
1062 #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */
1063 #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */
1065 #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
1109 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1110 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1111 #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */
1112 #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */
1113 #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */
1118 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1119 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1131 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1132 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
1136 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1200 /* DOE Data Object - note not actually registers */