Lines Matching full:invalidation

731  * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
733  * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
734  * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3
743  *                                           stage-1 cache invalidation
744  * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
753  * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
761  * The Intel VT-d specific invalidation data for user-managed stage-1 cache
762  * invalidation in nested translation. Userspace uses this structure to
778  * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
780  * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
802  * @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation
803  * @data_uptr: User pointer to an array of driver-specific cache invalidation
806  *             type of all the entries in the invalidation request array. It
809  * @entry_num: Input the number of cache invalidation requests in the array.
818  * Each ioctl can support one or more cache invalidation requests in the array
821  * An empty invalidation request array by setting @entry_num==0 is allowed, and
958  * - Non-device-affiliated event reporting, e.g. invalidation queue errors
961  * - Delivery of paravirtualized invalidation
962  * - Direct assigned invalidation queues