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39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
46 * format and data layout of the buffer, and should be the only way to describe
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
114 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1…
117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
120 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1…
128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
131 /* 1 bpp Red (direct relationship between channel value and brightness) */
132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1…
140 /* 8 bpp Red (direct relationship between channel value and brightness) */
141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
150 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
160 /* 8 bpp RGB */
161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian…
166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian…
167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian…
168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian…
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
175 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian…
176 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian…
177 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian…
178 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian…
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
185 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
186 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
214 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 littl…
215 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 littl…
217 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
218 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
222 * IEEE 754-2008 binary16 half-precision float
223 * [15:0] sign:exponent:mantissa 1:5:10
232 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
235 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
238 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
239 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
240 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
241 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
243 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
244 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
245 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
246 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endi…
247 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
248 …e DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-li…
252 * 16-xx padding occupy lsb
254 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:…
255 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:…
256 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16…
260 * 16-xx padding occupy lsb except Y410
262 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
263 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
264 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
266 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
267 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4…
268 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
274 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
276 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
279 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
281 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
285 * 1-plane YUV 4:2:0
287 * then V), but the exact Linear layout is undefined.
288 * These formats can only be used with a non-Linear modifier.
290 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
291 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
296 * index 1 = A plane, [7:0] A
298 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
299 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
300 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
301 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
302 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
303 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
304 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
305 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
310 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
312 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
314 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
315 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
316 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
317 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
318 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
323 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
325 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
326 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
327 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
332 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
334 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
339 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
341 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
346 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
348 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
353 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
355 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
360 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
364 /* 3 plane non-subsampled (444) YCbCr
365 * 16 bits per component, but only 10 bits are used and 6 bits are padded
367 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
370 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
372 /* 3 plane non-subsampled (444) YCrCb
373 * 16 bits per component, but only 10 bits are used and 6 bits are padded
375 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
378 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
383 * index 1: Cb plane, [7:0] Cb
386 * index 1: Cr plane, [7:0] Cr
389 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) plane…
390 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) plane…
391 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) plane…
392 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) plane…
393 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) plane…
394 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) plane…
395 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) plane…
396 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) plane…
397 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
398 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
404 * Format modifiers describe, typically, a re-ordering or modification
408 * The upper 8 bits of the format modifier are a vendor-id as assigned
427 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
447 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
449 * compatibility, in cases where a vendor-specific definition already exists and
453 * Note that generic names should only be used for modifiers which describe
454 * generic layouts (such as pixel re-ordering), which may have
455 * independently-developed support across multiple vendors.
458 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
459 * 'NONE' could be considered. This should only be for obvious, exceptional
460 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
485 * which tells the driver to also take driver-internal information into account
495 * used is out-of-band information carried in an API-specific way (e.g. in a
503 * Intel X-tiling layout
506 * in row-major layout. Within the tile bytes are laid out row-major, with
507 * a platform-dependent stride. On top of that the memory can apply
508 * platform-depending swizzling of some higher address bits into bit6.
510 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
512 * cross-driver sharing. It exists since on a given platform it does uniquely
513 * identify the layout in a simple way for i915-specific userspace, which
517 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
520 * Intel Y-tiling layout
523 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
524 * chunks column-major, with a platform-dependent height. On top of that the
525 * memory can apply platform-depending swizzling of some higher address bits
528 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
530 * cross-driver sharing. It exists since on a given platform it does uniquely
531 * identify the layout in a simple way for i915-specific userspace, which
538 * Intel Yf-tiling layout
540 * This is a tiled layout using 4Kb tiles in row-major layout.
541 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
542 * are arranged in four groups (two wide, two high) with column-major layout.
544 * out as 2x2 column-major.
546 * either a square block or a 2:1 unit.
555 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
556 * The main surface will be plane index 0 and must be Y/Yf-tiled,
557 * the CCS will be plane index 1.
565 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
573 * Intel color control surfaces (CCS) for Gen-12 render compression.
575 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
576 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
579 * Y-tile widths.
584 * Intel color control surfaces (CCS) for Gen-12 media compression
586 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
587 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
590 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
591 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
597 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
600 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
601 * and at index 1. The clear color is stored at index 2, and the pitch should
613 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
620 * only differs from Tile Y at the 256B granularity in between. At this
622 * of 64B x 8 rows.
639 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
641 * 0 and 1, respectively. The CCS for all planes are stored outside of the
655 * clear color is stored at plane index 1 and the pitch should be 64 bytes
666 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
677 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
680 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
681 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
691 * and at index 1. The clear color is stored at index 2, and the pitch should
709 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
711 * 0 and 1, respectively. The CCS for all planes are stored outside of the
721 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
723 * 0 and 1, respectively. The CCS for all planes are stored outside of the
731 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
733 * Macroblocks are laid in a Z-shape, and each pixel data is following the
736 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
738 * - multiple of 128 pixels for the width
739 * - multiple of 32 pixels for the height
741 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
743 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
746 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
748 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
758 * Implementation may be platform and base-format specific.
765 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
771 * Implementation may be platform and base-format specific.
783 * Alternate tiled format typically only used within GMEM.
784 * Implementation may be platform and base-format specific.
794 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
797 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
800 * Vivante 64x64 super-tiling layout
802 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
803 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
807 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
812 * Vivante 4x4 tiling layout for dual-pipe
816 * compared to the non-split tiled layout.
821 * Vivante 64x64 super-tiling layout for dual-pipe
823 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
825 * therefore halved compared to the non-split super-tiled layout.
830 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
836 * We reserve the top 8 bits of the Vivante modifier space for tile status
840 #define VIVANTE_MOD_TS_64_4 (1ULL << 48)
851 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
865 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
882 * ---- ----- -----------------------------------------------------------------
886 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
888 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
890 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
892 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
900 * 11:9 - Reserved (To support 2D-array textures with variable array stride
921 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
922 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
923 * 2 = Gob Height 8, Turing+ Page Kind mapping
932 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
933 * 1 = Desktop GPU and Tegra Xavier+ Layout
938 * 1 = ROP/3D, layout 1, exact compression format implied by Page
948 * 55:25 - Reserved for future use. Must be zero.
960 * with block-linear layouts, is remapped within drivers to the value 0xfe,
961 * which corresponds to the "generic" kind used for simple single-sample
962 * uncompressed color formats on Fermi - Volta GPUs.
977 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
979 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
981 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
985 * 1 == TWO_GOBS
994 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ argument
995 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
1000 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
1013 * type, and the next 24 bits for parameters. Top 8 bits are the
1016 #define __fourcc_mod_broadcom_param_shift 8
1022 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1024 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1033 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1036 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1039 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1043 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1044 * tiles) or right-to-left (odd rows of 4k tiles).
1046 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
1052 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
1057 * only 128 pixel columns are used.
1067 * and UV. Some SAND-using hardware stores UV in a separate tiled
1076 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ argument
1077 fourcc_mod_broadcom_code(2, v)
1078 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ argument
1079 fourcc_mod_broadcom_code(3, v)
1080 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ argument
1081 fourcc_mod_broadcom_code(4, v)
1082 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ argument
1083 fourcc_mod_broadcom_code(5, v)
1111 * the assumption is that a no-XOR tiling modifier will be created.
1119 * It provides fine-grained random access and minimizes the amount of data
1124 * and different devices or use-cases may support different combinations.
1156 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1159 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
1170 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1173 * AFBC block-split
1179 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1191 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1194 * AFBC copy-block restrict
1196 * Buffers with this flag must obey the copy-block restriction. The restriction
1197 * is such that there are no copy-blocks referring across the border of 8x8
1198 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1200 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1205 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1206 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1212 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1217 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1220 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1223 * AFBC double-buffer
1225 * Indicates that the buffer is allocated in a layout safe for front-buffer
1228 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1233 * Indicates that the buffer includes per-superblock content hints.
1235 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1241 * storage mode, which is usually only used for data which cannot be compressed.
1242 * The buffer layout is the same as for AFBC buffers without USM set, this only
1247 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1250 * Arm Fixed-Rate Compression (AFRC) modifiers
1254 * reductions in graphics and media use-cases.
1270 * ---------------- ---------------
1281 * ------ ----------------- ------------------
1283 * ROT 8 coding units 8 coding units
1290 * ----------------------------- --------- ----------------- ------------------
1291 * 1 SCAN 16 samples 4 samples
1293 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1294 * ----------------------------- --------- ----------------- ------------------
1295 * 1 ROT 8 samples 8 samples
1296 * Example: 8x8 luma samples in a 'Y' plane
1297 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1298 * ----------------------------- --------- ----------------- ------------------
1299 * 2 DONT CARE 8 samples 4 samples
1300 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1301 * ----------------------------- --------- ----------------- ------------------
1304 * ----------------------------- --------- ----------------- ------------------
1323 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1328 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1330 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1332 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1336 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1346 * Indicates if the buffer uses the scanline-optimised layout
1347 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1350 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1353 * Arm 16x16 Block U-Interleaved modifier
1360 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1372 * both in row-major order.
1374 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1386 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1388 * - DRM_FORMAT_YUV420_8BIT
1389 * - DRM_FORMAT_YUV420_10BIT
1391 * The first 8 bits of the mode defines the layout, then the following 8 bits
1398 #define __fourcc_mod_amlogic_options_shift 8
1413 * - a body content organized in 64x32 superblocks with 4096 bytes per
1415 * - a 32 bytes per 128x64 header block
1419 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1427 * In this mode, only the header memory address is needed, thus the
1433 * be accessible by the user-space clients, but only accessible by the
1436 * The user-space clients should expect a failure while trying to mmap
1437 * the DMA-BUF handle returned by the producer.
1447 * boundaries, i.e. 8bit should be stored in this mode to save allocation
1454 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1462 * - main surface
1465 * - main surface in plane 0
1466 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1469 * - main surface in plane 0
1470 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1471 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1473 * For multi-plane formats the above surfaces get merged into one plane for
1474 * each format plane, based on the required alignment only.
1477 * ----- ------------------------ ---------------------------------------------
1480 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1488 * 23:21 PIPE_XOR_BITS Only for some chips
1489 * 26:24 BANK_XOR_BITS Only for some chips
1490 * 29:27 PACKERS Only for some chips
1491 * 32:30 RB Only for some chips
1492 * 35:33 PIPE Only for some chips
1493 * 55:36 - Reserved for future use, must be zero
1500 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1513 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1526 * 0 - LINEAR
1527 * 1 - 256B_2D - 2D block dimensions
1528 * 2 - 4KB_2D
1529 * 3 - 64KB_2D
1530 * 4 - 256KB_2D
1531 * 5 - 4KB_3D - 3D block dimensions
1532 * 6 - 64KB_3D
1533 * 7 - 256KB_3D
1535 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
1541 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1546 #define AMD_FMT_MOD_TILE_SHIFT 8
1555 * one which is not-aligned.
1560 /* Only set if DCC_RETILE = false */
1584 * The below fields are for accounting for per GPU differences. These are only
1588 * BANK_XOR_BITS = only for TILE_VER_GFX9
1589 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1590 * RB = only for TILE_VER_GFX9 & DCC
1591 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)