Lines Matching defs:hdac_bus

291 struct hdac_bus {  struct
293 	const struct hdac_bus_ops *ops;  argument
294 	const struct hdac_ext_bus_ops *ext_ops;
297 	unsigned long addr;
298 	void __iomem *remap_addr;
299 	int irq;
301 	void __iomem *ppcap;
302 	void __iomem *spbcap;
303 	void __iomem *mlcap;
304 	void __iomem *gtscap;
305 	void __iomem *drsmcap;
308 	struct list_head codec_list;
309 	unsigned int num_codecs;
312 	struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
315 	u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
316 	unsigned int unsol_rp, unsol_wp;
317 	struct work_struct unsol_work;
320 	unsigned long codec_mask;
323 	unsigned long codec_powered;
326 	struct hdac_rb corb;
327 	struct hdac_rb rirb;
328 	unsigned int last_cmd[HDA_MAX_CODECS];	/* last sent command */
329 	wait_queue_head_t rirb_wq;
332 	struct snd_dma_buffer rb;
333 	struct snd_dma_buffer posbuf;
334 	int dma_type;			/* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
337 	struct list_head stream_list;
340 	bool chip_init:1;		/* h/w initialized */
343 	bool aligned_mmio:1;		/* aligned MMIO access */
344 	bool sync_write:1;		/* sync after verb write */
345 	bool use_posbuf:1;		/* use position buffer */
346 	bool snoop:1;			/* enable snooping */
347 	bool align_bdle_4k:1;		/* BDLE align 4K boundary */
348 	bool reverse_assign:1;		/* assign devices in reverse order */
349 	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */
350 	bool polling_mode:1;
351 	bool needs_damn_long_delay:1;
352 	bool not_use_interrupts:1;	/* prohibiting the RIRB IRQ */
353 	bool access_sdnctl_in_dword:1;	/* accessing the sdnctl register by dword */
354 	bool use_pio_for_commands:1;	/* Use PIO instead of CORB for commands */
356 	int poll_count;
358 	int bdl_pos_adj;		/* BDL position adjustment */
361 	unsigned int dma_stop_delay;
385 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,  argument