Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * HD-audio controller (Azalia) registers and helpers
15 #define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
16 #define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
25 #define AZX_GCTL_RESET (1 << 0) /* controller reset */
26 #define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
27 #define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
31 #define AZX_GSTS_FSTS (1 << 1) /* flush status */
45 #define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
47 #define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
48 #define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
50 #define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
56 #define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
59 #define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
60 #define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
61 #define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
63 #define AZX_RBSTS_IRQ (1 << 0) /* response irq */
64 #define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
70 #define AZX_IRS_VALID (1<<1)
71 #define AZX_IRS_BUSY (1<<0)
109 /* Haswell/Broadwell display HD-A controller Extended Mode registers */
113 /* Skylake/Broxton vendor-specific registers */
143 /* max number of fragments - we may use more if allocating more pages for BDL */
148 * max buffer size - artificial 4MB limit per stream to avoid big allocations
160 #define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)
163 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
164 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
166 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
167 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
184 #define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
185 #define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
187 /* below are so far hardcoded - should read registers in future */
225 #define AZX_PPCTL_PIE (1<<31)
226 #define AZX_PPCTL_GPROCEN (1<<30)
228 #define AZX_PPCTL_PROCEN(_X_) (1<<(_X_))
248 (((1 << (bit_num)) - 1) << (offset))
251 #define AZX_PPLCCTL_RUN (1<<1)
252 #define AZX_PPLCCTL_STRST (1<<0)
268 #define AZX_ML_HDA_LCAP_ALT BIT(28)
272 #define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */
273 #define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */
274 #define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */
275 #define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */
278 #define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */
279 #define AZX_ML_LCTL_CPA BIT(23)
281 #define AZX_ML_LCTL_SPA BIT(16)
283 #define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */
284 #define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */
285 #define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */
289 /* bit0 is reserved, with BIT(1) mapping to stream1 */
293 #define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */
295 /* HDaudio registers only valid if LCAP.ALT == 0 */
302 /* HDaudio Extended link registers only valid if LCAP.ALT == 1 */
305 #define AZX_REG_ML_LSYNC_CMDSYNC BIT(24)
307 #define AZX_REG_ML_LSYNC_SYNCGO BIT(23)
308 #define AZX_REG_ML_LSYNC_SYNCPU BIT(20)
332 #define GTSCC_TSCCD_SHIFT BIT(31)
365 return le32_to_cpu(*stream->posbuf); in snd_hdac_stream_get_pos_posbuf()