Lines Matching full:pdif
229 /* I2S0 can phase track the last S/PDIF input */
736 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
845 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
846 #define A_SPRA 0x6b /* S/PDIF Host Record Address */
847 #define A_SPRC 0x6c /* S/PDIF Host Record Control */
970 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
971 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
1163 * 0x1a: S/PDIF Left
1165 * 0x1e: S/PDIF Right
1166 * 0x02, 0x00: Hana S/PDIF Left
1167 * 0x02, 0x01: Hana S/PDIF Right
1189 * 0x12: Dock S/PDIF Left
1191 * 0x16: Dock S/PDIF Right
1193 * 0x02, 0x00: Hana3 S/PDIF Left
1194 * 0x02, 0x01: Hana3 S/PDIF Right
1205 * 0x02, 0x00: S/PDIF Left
1206 * 0x02, 0x01: S/PDIF Right
1312 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1313 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1314 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1315 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1316 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1340 * 0x05, 0x00: Hana S/PDIF Left
1341 * 0x05, 0x01: Hana S/PDIF Right
1355 * 0x12: Dock S/PDIF Left
1357 * 0x16: Dock S/PDIF Right
1364 * 0x05, 0x00: Hana3 S/PDIF Left
1365 * 0x05, 0x01: Hana3 S/PDIF Right
1377 * 0x05, 0x00: S/PDIF Left
1378 * 0x05, 0x01: S/PDIF Right
1452 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1453 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
1454 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1455 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
1731 unsigned int spdif_bits[3]; /* s/pdif out setup */