1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
50 #define QM_PIRQ_DQRI	0x00020000	/* DQRR Ring (non-empty) */
51 #define QM_PIRQ_MRI	0x00010000	/* MR Ring (non-empty) */
54  * ie. that if present should trigger slow-path processing.
66 	return QM_SDQCR_CHANNELS_POOL(channel + 1 - qm_channel_pool1);  in QM_SDQCR_CHANNELS_POOL_CONV()
69 /* --- QMan data structures (and associated constants) --- */
78 			u8 addr_hi;	/* high 8-bits of 40-bit address */
79 			__be32 addr_lo;	/* low 32-bits of 40-bit address */
102 	 * scatter-gather table. 'big' implies a 29-bit length with no offset
103 	 * field, otherwise length is 20-bit and offset is 9-bit. 'compound'
104 	 * implies a s/g-like table, where each entry itself represents a frame
105 	 * (contiguous or scatter-gather) and the 29-bit "length" is
118 	return be64_to_cpu(fd->data) & 0xffffffffffLLU;  in qm_fd_addr()
123 	return be64_to_cpu(fd->data) & 0xffffffffffLLU;  in qm_fd_addr_get64()
128 	fd->addr_hi = upper_32_bits(addr);  in qm_fd_addr_set64()
129 	fd->addr_lo = cpu_to_be32(lower_32_bits(addr));  in qm_fd_addr_set64()
134  * 29 bits of the 32-bit word.
141 	return be32_to_cpu(fd->cfg) & QM_FD_FORMAT_MASK;  in qm_fd_get_format()
146 	return (be32_to_cpu(fd->cfg) & QM_FD_OFF_MASK) >> QM_FD_OFF_SHIFT;  in qm_fd_get_offset()
151 	return be32_to_cpu(fd->cfg) & QM_FD_LEN_MASK;  in qm_fd_get_length()
156 	return be32_to_cpu(fd->cfg) & QM_FD_LEN_BIG_MASK;  in qm_fd_get_len_big()
162 	fd->cfg = cpu_to_be32(fmt | (len & QM_FD_LEN_BIG_MASK) |  in qm_fd_set_param()
176 	fd->data = 0;  in qm_fd_clear_fd()
177 	fd->cfg = 0;  in qm_fd_clear_fd()
178 	fd->cmd = 0;  in qm_fd_clear_fd()
186 			u8 addr_hi;	/* high 8-bits of 40-bit address */
187 			__be32 addr_lo;	/* low 32-bits of 40-bit address */
194 	__be16 offset; /* 13-bit, _res[13-15]*/
204 	return be64_to_cpu(sg->data) & 0xffffffffffLLU;  in qm_sg_addr()
209 	return be64_to_cpu(sg->data) & 0xffffffffffLLU;  in qm_sg_entry_get64()
214 	sg->addr_hi = upper_32_bits(addr);  in qm_sg_entry_set64()
215 	sg->addr_lo = cpu_to_be32(lower_32_bits(addr));  in qm_sg_entry_set64()
220 	return be32_to_cpu(sg->cfg) & QM_SG_FIN;  in qm_sg_entry_is_final()
225 	return be32_to_cpu(sg->cfg) & QM_SG_EXT;  in qm_sg_entry_is_ext()
230 	return be32_to_cpu(sg->cfg) & QM_SG_LEN_MASK;  in qm_sg_entry_get_len()
235 	sg->cfg = cpu_to_be32(len & QM_SG_LEN_MASK);  in qm_sg_entry_set_len()
240 	sg->cfg = cpu_to_be32(QM_SG_FIN | (len & QM_SG_LEN_MASK));  in qm_sg_entry_set_f()
245 	return be16_to_cpu(sg->offset) & QM_SG_OFF_MASK;  in qm_sg_entry_get_off()
252 	__be16 seqnum;	/* 15-bit */
255 	__be32 fqid;	/* 24-bit */
264 #define QM_DQRR_STAT_FQ_HELDACTIVE	0x40	/* FQ held active */
265 #define QM_DQRR_STAT_FQ_FORCEELIGIBLE	0x20	/* FQ was force-eligible'd */
266 #define QM_DQRR_STAT_FD_VALID		0x10	/* has a non-NULL FD */
270 /* 'fqid' is a 24-bit field in every h/w descriptor */
272 #define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
273 #define qm_fqid_get(p)    (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
286 		u8 rc;		/* Rej Code: 8-bit */
288 		__be32 fqid;	/* 24-bit */
297 		__be32 fqid;	/* 24-bit */
304  * ERNs originating from direct-connect portals ("dcern") use 0x20 as a verb
337 	u8 cl; /* _res[6-7], as[4-5], ds[2-3], cs[0-1] */
342 	u8 oac; /* oac[6-7], _res[0-5] */
343 	/* Two's-complement value (-128 to +127) */
348 	/* _res[6-7], orprws[3-5], oa[2], olws[0-1] */
352 	__be16 dest_wq;	/* channel[3-15], wq[0-2] */
353 	__be16 ics_cred; /* 15-bit */
355 	 * For "Initialize Frame Queue" commands, the write-enable mask
361 		__be16 td; /* "Taildrop": _res[13-15], mant[5-12], exp[0-4] */
366 		/* Treat it as 64-bit opaque */
377 			 * 48-bit address of FQ context to
378 			 * stash, must be cacheline-aligned
399 /* 64-bit converters for context_hi/lo */
402 	return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL;  in qm_fqd_stashing_get64()
407 	return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL;  in qm_fqd_stashing_addr()
417 	fqd->context_a.context_hi = cpu_to_be16(upper_32_bits(addr));  in qm_fqd_stashing_set64()
418 	fqd->context_a.context_lo = cpu_to_be32(lower_32_bits(addr));  in qm_fqd_stashing_set64()
423 	fqd->context_a.hi = cpu_to_be32(upper_32_bits(addr));  in qm_fqd_context_a_set64()
424 	fqd->context_a.lo = cpu_to_be32(lower_32_bits(addr));  in qm_fqd_context_a_set64()
435 		return -ERANGE;  in qm_fqd_set_taildrop()
447 	fqd->td = cpu_to_be16(td);  in qm_fqd_set_taildrop()
453 	int td = be16_to_cpu(fqd->td);  in qm_fqd_get_taildrop()
461 	struct qm_fqd_stashing *st = &fqd->context_a.stashing;  in qm_fqd_set_stashing()
463 	st->cl = ((as & QM_FQD_XS_MASK) << QM_FQD_AS_OFF) |  in qm_fqd_set_stashing()
470 	return fqd->context_a.stashing.cl;  in qm_fqd_get_stashing()
475 	fqd->oac_init.oac = val << QM_FQD_OAC_OFF;  in qm_fqd_set_oac()
480 	fqd->oac_init.oal = val;  in qm_fqd_set_oal()
485 	fqd->dest_wq = cpu_to_be16((ch << QM_FQD_CHAN_OFF) |  in qm_fqd_set_destwq()
491 	return be16_to_cpu(fqd->dest_wq) >> QM_FQD_CHAN_OFF;  in qm_fqd_get_chan()
496 	return be16_to_cpu(fqd->dest_wq) & QM_FQD_WQ_MASK;  in qm_fqd_get_wq()
503 #define QM_FQCTRL_TDE		0x0200	/* Tail-Drop Enable */
504 #define QM_FQCTRL_CTXASTASHING	0x0080	/* Context-A stashing */
506 #define QM_FQCTRL_FORCESFDR	0x0008	/* High-priority SFDRs */
507 #define QM_FQCTRL_AVOIDBLOCK	0x0004	/* Don't block active */
508 #define QM_FQCTRL_HOLDACTIVE	0x0002	/* Hold active in portal */
520 #define QM_OAC_ICS		0x2 /* Accounting for Intra-Class Scheduling */
524  * This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields
532 	/* MA[24-31], Mn[19-23], SA[12-18], Sn[6-11], Pn[0-5] */
536  * This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding
537  * management commands, this is padded to a 16-bit structure field, so that's
543 	/* _res[13-15], TA[5-12], Tn[0-4] */
574 #define QM_CGR_TARG_PORTAL(n)	(0x80000000 >> (n)) /* s/w portal, 0-9 */
575 #define QM_CGR_TARG_FMAN0	0x00200000 /* direct-connect portal: fman0 */
580 	int thres = be16_to_cpu(th->word);  in qm_cgr_cs_thres_get64()
598 	th->word = cpu_to_be16(((val & 0xff) << 5) | (e & 0x1f));  in qm_cgr_cs_thres_set64()
606 	__be32 fqid;	/* 24-bit */
621 /* INITFQ-specific flags */
632 /* INITCGR/MODIFYCGR-specific flags */
655  * cacheline-aligned, and initialised by qman_create_fq(). The structure is
675 	/* Like _consume, but requests parking - FQ must be held-active */
681 	 * qman_p_poll_dqrr() or interrupt-handling, as appropriate. If within
703  * s/w-visible states. Ie. tentatively scheduled + truly scheduled + active +
704  * held-active + held-suspended are just "sched". Things like "retired" will not
730  * qman_create_fq(), as this allows stashing of caller-provided demux callback
731  * pointers at no extra cost to stashing of (driver-internal) FQ state. If the
732  * caller wishes to add per-FQ state and have it benefit from dequeue-stashing,
743  *     struct qman_fq *fq = qman_create_fq(fqid, flags, &myfq->base);
747  *     do_something_with(myfq->an_extra_field);
758 	qman_cb_mr fqs;		/* frame-queue state changes*/
777  * 'congested' is non-zero on congestion-entry, and zero on congestion-exit.
784 	u32 cgrid; /* 0..255, but u32 to allow specials like -1, 256, etc.*/
794 #define QMAN_FQ_FLAG_TO_DCPORTAL     0x00000004 /* consumed by CAAM/PME/Fman */
803  * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
818 /* "Query FQ Non-Programmable Fields" */
824 	u32 fqd_link;		/* 24-bit, _res2[24-31] */
825 	u16 odp_seq;		/* 14-bit, _res3[14-15] */
826 	u16 orp_nesn;		/* 14-bit, _res4[14-15] */
827 	u16 orp_ea_hseq;	/* 15-bit, _res5[15] */
828 	u16 orp_ea_tseq;	/* 15-bit, _res6[15] */
829 	u32 orp_ea_hptr;	/* 24-bit, _res7[24-31] */
830 	u32 orp_ea_tptr;	/* 24-bit, _res8[24-31] */
831 	u32 pfdr_hptr;		/* 24-bit, _res9[24-31] */
832 	u32 pfdr_tptr;		/* 24-bit, _res10[24-31] */
834 	u8 is;			/* 1-bit, _res12[1-7] */
837 	u32 frm_cnt;		/* 24-bit, _res13[24-31] */
863 	qm_mcr_fqd_link_mask = BIT(24) - 1,
864 	qm_mcr_odp_seq_mask = BIT(14) - 1,
865 	qm_mcr_orp_nesn_mask = BIT(14) - 1,
866 	qm_mcr_orp_ea_hseq_mask = BIT(15) - 1,
867 	qm_mcr_orp_ea_tseq_mask = BIT(15) - 1,
868 	qm_mcr_orp_ea_hptr_mask = BIT(24) - 1,
869 	qm_mcr_orp_ea_tptr_mask = BIT(24) - 1,
870 	qm_mcr_pfdr_hptr_mask = BIT(24) - 1,
871 	qm_mcr_pfdr_tptr_mask = BIT(24) - 1,
872 	qm_mcr_is_mask = BIT(1) - 1,
873 	qm_mcr_frm_cnt_mask = BIT(24) - 1,
877 	((np)->field & (qm_mcr_##field##_mask))
881  * qman_p_irqsource_add - add processing sources to be interrupt-driven
884  * Adds processing sources that should be interrupt-driven (rather than
890  * qman_p_irqsource_remove - remove processing sources from being int-driven
893  * Removes processing sources from being interrupt-driven, so that they will
899  * qman_affine_cpus - return a mask of cpus that have affine portals
904  * qman_affine_channel - return the channel ID of an portal
907  * If @cpu is -1, the affine portal for the current CPU will be used. It is a
908  * bug to call this function for any value of @cpu (other than -1) that is not a
914  * qman_get_affine_portal - return the portal pointer affine to cpu
920  * qman_start_using_portal - register a device link for the portal user
930  * qman_p_poll_dqrr - process DQRR (fast-path) entries
933  * Use of this function requires that DQRR processing not be interrupt-driven.
939  * qman_p_static_dequeue_add - Add pool channels to the portal SDQCR
940  * @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n)
950  * qman_create_fq - Allocates a FQ
952  * @flags: bit-mask of QMAN_FQ_FLAG_*** options
959  * adjacent memory for user-defined fields (see the definition of "struct
961  * pre-existing frame-queues that aren't to be otherwise interfered with, it
965  * direct-connect portal (PME, CAAM, or Fman). When frame queues are consumed by
972  * qman_destroy_fq - Deallocates a FQ
977  * FQ must be in the 'out-of-service' or in the 'parked' state.
982  * qman_fq_fqid - Queries the frame queue ID of a FQ object
988  * qman_init_fq - Initialises FQ fields, leaves the FQ "parked" or "scheduled"
990  * @flags: bit-mask of QMAN_INITFQ_FLAG_*** options
991  * @opts: the FQ-modification settings, as defined in the low-level API
993  * The @opts parameter comes from the low-level portal API. Select
1003  *   - if @fq was not created with QMAN_FQ_FLAG_TO_DCPORTAL, then context_b is
1005  *   - if context_b is initialised for demux, so is context_a in case stashing
1011  * the command. If the WE_DESTWQ write-enable bit had already been set by the
1012  * caller, the channel workqueue will be left as-is, otherwise the write-enable
1014  * isn't set, the destination channel/workqueue fields and the write-enable bit
1015  * are left as-is.
1024  * qman_schedule_fq - Schedules a FQ
1028  * Tentatively-Scheduled or Truly-Scheduled depending on its fill-level.
1033  * qman_retire_fq - Retires a FQ
1045  * Active state), the completion will be via the message ring as a FQRN - but
1053  * qman_oos_fq - Puts a FQ "out of service"
1054  * @fq: the frame queue object to be put out-of-service, must be 'retired'
1062  * qman_volatile_dequeue - Issue a volatile dequeue command
1064  * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
1069  * the VDQCR is already in use, otherwise returns non-zero for failure. If
1081  * qman_enqueue - Enqueue a frame to a frame queue
1087  * field is ignored. The return value is non-zero on error, such as ring full.
1092  * qman_alloc_fqid_range - Allocate a contiguous range of FQIDs
1102  * qman_release_fqid - Release the specified frame queue ID
1112  * qman_query_fq_np - Queries non-programmable FQD fields
1118 	/* Pool-channel management */
1120  * qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs
1121  * @result: is set by the API to the base pool-channel ID of the allocated range
1122  * @count: the number of pool-channel IDs required
1130  * qman_release_pool - Release the specified pool-channel ID
1131  * @id: the pool-chan ID to be released back to the resource pool
1134  * pool-channel ID ranges that it can subsequently allocate from.
1141  * qman_create_cgr - Register a congestion group object
1148  * NULL then only the callback (cgr->cb) function is registered. If @flags
1157  * qman_delete_cgr - Deregisters a congestion group object
1167  * qman_delete_cgr_safe - Deregisters a congestion group object from any CPU
1175  * qman_update_cgr_safe - Modifies a congestion group object from any CPU
1184  * qman_query_cgr_congested - Queries CGR's congestion status
1191  * qman_alloc_cgrid_range - Allocate a contiguous range of CGR IDs
1201  * qman_release_cgrid - Release the specified CGR ID
1211  * qman_is_probed - Check if qman is probed
1213  * Returns 1 if the qman driver successfully probed, -1 if the qman driver
1219  * qman_portals_probed - Check if all cpu bound qman portals are probed
1222  * -1 if probe errors appeared or 0 if the qman portals did not yet finished
1228  * qman_dqrr_get_ithresh - Get coalesce interrupt threshold
1235  * qman_dqrr_set_ithresh - Set coalesce interrupt threshold
1244  * qman_dqrr_get_iperiod - Get coalesce interrupt period
1251  * qman_dqrr_set_iperiod - Set coalesce interrupt period