Lines Matching +full:qe +full:- +full:firmware
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * QUICC Engine (QE) external definitions and structure.
21 #include <soc/fsl/qe/immap_qe.h>
28 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
87 /* Export QE common operations */
112 return -ENOSYS; in cpm_muram_alloc()
118 return -ENOSYS; in devm_cpm_muram_alloc()
128 return -ENOSYS; in cpm_muram_alloc_fixed()
135 return -ENOSYS; in devm_cpm_muram_alloc_fixed()
145 return -ENOSYS; in cpm_muram_offset()
157 /* QE PIO */
184 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } in par_io_init()
185 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } in par_io_of_config()
187 int assignment, int has_irq) { return -ENOSYS; } in par_io_config_pin()
188 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } in par_io_data_set()
203 return ERR_PTR(-ENOSYS); in qe_pin_request()
216 return -ENOSYS; in qe_issue_cmd()
220 /* QE internal API */
279 /* Structure that defines QE firmware binary files.
290 u8 id[62]; /* Null-terminated identifier string */
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
303 u8 id[32]; /* Null-terminated identifier */
306 __be32 iram_offset; /* Offset into I-RAM for the code */
307 __be32 count; /* Number of 32-bit words of the code */
320 char id[64]; /* Firmware name */
326 /* Upload a firmware to the QE */
327 int qe_upload_firmware(const struct qe_firmware *firmware);
329 static inline int qe_upload_firmware(const struct qe_firmware *firmware) in qe_upload_firmware() argument
331 return -ENOSYS; in qe_upload_firmware()
335 /* Obtain information on the uploaded firmware */
338 /* QE USB */
368 /* QE extended filtering Table Lookup Key Size */
378 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
388 /* structure representing QE parameter RAM */
390 u16 tm_base; /* QE timer table base adr */
391 u16 tm_ptr; /* QE timer table pointer */
392 u16 r_tmr; /* QE timer mode register */
393 u16 r_tmv; /* QE timer valid register */
394 u32 tm_cmd; /* QE timer cmd register */
395 u32 tm_cnt; /* QE timer internal cnt */
400 /* QE extended filtering Termination Action Descriptor (TAD) */
413 /* QE CMXUCR Registers.
424 /* QE CMXGCR Registers.
440 /* QE CECR Commands.
495 /* QE CECR Sub Block - sub block of QE command.
529 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
544 /* QE Timers registers */
578 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
582 /* I-RAM */