Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0-only */
23 #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
24 #define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
49 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
50 #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
51 #define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-…
58 …_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
62 #define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
66 #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
68 #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
70 #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
73 #define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
74 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset …
76 #define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */
79 #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
82 #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
83 #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
84 #define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */
85 #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
86 #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */