Lines Matching +full:one +full:- +full:timer +full:- +full:only

2  * Timer/Counter Unit (TC) registers.
17  * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18  * three general-purpose 16-bit timers.  These timers share one register bank.
19  * Depending on the SOC, each timer may have its own clock and IRQ, or those
23  * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37  * struct atmel_tcb_config - SoC data for a Timer/Counter Block
38  * @counter_width: size in bits of a timer counter register
39  * @has_gclk: boolean indicating if a timer counter has a generic clock
40  * @has_qdec: boolean indicating if a timer counter has a quadrature
50  * struct atmel_tc - information about a Timer/Counter Block
80 /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
85  * Two registers have block-wide controls.  These are: configuring the three
86  * "external" clocks (or event sources) used by the timer channels; and
90  * signals.  Or, it can mean "external to timer", using the TIOA output from
91  * one of the other two timers that's being run in waveform mode.
116  * Each TC block has three "channels", each with one counter and controls.
119  * when it's not "external") is silicon-specific.  AT91 platforms use one
120  * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
129  * Each timer has two I/O pins, TIOA and TIOB.  Waveform mode uses TIOA as a
131  * uses them only as inputs.
247 #define ATMEL_TC_SR	0x20		/* status (read-only) */
248 /* Status-only flags */
253 #define ATMEL_TC_IER	0x24		/* interrupt enable (write-only) */
254 #define ATMEL_TC_IDR	0x28		/* interrupt disable (write-only) */
255 #define ATMEL_TC_IMR	0x2c		/* interrupt mask (read-only) */