Lines Matching +full:layer +full:- +full:base +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0+
14 * reuse common code. A bit like a in-kernel library.
22 int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
32 u8 pp_mmio_bar; /* per-process MMIO area */
44 int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
45 int dvsec_function_pos; /* offset of the Function DVSEC */
46 int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
52 OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
53 OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
65 * ocxl_function_open() - Open an OpenCAPI function on an OpenCAPI device
73 * ocxl_function_afu_list() - Get the list of AFUs associated with a PCI function device
81 * ocxl_function_fetch_afu() - Fetch an AFU instance from an OpenCAPI function
92 * ocxl_afu_get() - Take a reference to an AFU
98 * ocxl_afu_put() - Release a reference to an AFU
105 * ocxl_function_config() - Get the configuration information for an OpenCAPI function
113 * ocxl_function_close() - Close an OpenCAPI function
125 * ocxl_context_alloc() - Allocate an OpenCAPI context
134 * ocxl_context_free() - Free an OpenCAPI context
140 * ocxl_context_attach() - Grant access to an MM to an OpenCAPI context
151 * ocxl_context_detach() - Detach an MM from an OpenCAPI context
161 * ocxl_afu_irq_alloc() - Allocate an IRQ associated with an AFU context
170 * ocxl_afu_irq_free() - Frees an IRQ associated with an AFU context
179 * ocxl_afu_irq_get_addr() - Gets the address of the trigger page for an IRQ
190 * ocxl_irq_set_handler() - Provide a callback to be called when an IRQ is triggered
207 * ocxl_afu_config() - Get a pointer to the config for an AFU
215 * ocxl_afu_set_private() - Assign opaque hardware specific information to an OpenCAPI AFU.
222 * ocxl_afu_get_private() - Fetch the hardware specific information associated with
232 * ocxl_global_mmio_read32() - Read a 32 bit value from global MMIO
234 * @offset: The Offset from the start of MMIO
240 int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset,
244 * ocxl_global_mmio_read64() - Read a 64 bit value from global MMIO
246 * @offset: The Offset from the start of MMIO
252 int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset,
256 * ocxl_global_mmio_write32() - Write a 32 bit value to global MMIO
258 * @offset: The Offset from the start of MMIO
264 int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset,
268 * ocxl_global_mmio_write64() - Write a 64 bit value to global MMIO
270 * @offset: The Offset from the start of MMIO
276 int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset,
280 * ocxl_global_mmio_set32() - Set bits in a 32 bit global MMIO register
282 * @offset: The Offset from the start of MMIO
288 int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset,
292 * ocxl_global_mmio_set64() - Set bits in a 64 bit global MMIO register
294 * @offset: The Offset from the start of MMIO
300 int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset,
304 * ocxl_global_mmio_clear32() - Set bits in a 32 bit global MMIO register
306 * @offset: The Offset from the start of MMIO
312 int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset,
316 * ocxl_global_mmio_clear64() - Set bits in a 64 bit global MMIO register
318 * @offset: The Offset from the start of MMIO
324 int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset,
343 * 'afu_control_offset' is the offset of the AFU control DVSEC which
352 * 'base' is the first actag value that can be used.
353 * 'enabled' it the number of actags available, starting from base.
358 u16 *base, u16 *enabled, u16 *supported);
364 * 'func_offset' is the offset of the Function DVSEC that can found in
374 * 'afu_control_offset' is the offset of the AFU control DVSEC for the
384 * 'afu_control_offset' is the offset of the AFU control DVSEC for the
391 * Set the Transaction Layer configuration in the configuration space.
395 * between the host and device, and set the Transaction Layer on both
408 * 'afu_control_offset' is the offset of the AFU control DVSEC for the