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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
16 #define SAA7115_COMPOSITE1 1
27 #define SAA7115_IPORT_ON 1
39 * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
40 * controls the IDQ signal polarity which is set to 'inverted' if the bit
41 * it 1 and to 'default' if it is 0.
43 #define SAA7115_IDQ_IS_DEFAULT (1 << 0)
48 #define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
52 #define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
53 #define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
54 #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
55 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
59 /* Register 0x08 "Horizontal time constant" [Bit 3..4]:
69 /* Register 0x10 "Output format selection" [Bit 6..7]:
78 * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]:
80 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0)
81 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified
85 SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */
104 * struct saa7115_platform_data - Allow overriding default initialization
108 * (saa7113 only)
109 * @saa7113_r08_htc: [R_08 - Bit 3..4]
110 * @saa7113_r10_vrln: [R_10 - Bit 3]
113 * @saa7113_r10_ofts: [R_10 - Bit 6..7]
114 * @saa7113_r12_rts0: [R_12 - Bit 0..3]
115 * @saa7113_r12_rts1: [R_12 - Bit 4..7]
116 * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled