Lines Matching +full:pin +full:- +full:settings
1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
215 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
226 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
230 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
232 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
238 #define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
242 #define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
243 #define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
244 #define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
245 #define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
246 #define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
247 #define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
254 #define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
255 #define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
256 #define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
271 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
282 #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
283 #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
286 #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
287 #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
289 #define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
296 #define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
298 #define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
410 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
411 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
414 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
415 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
420 #define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
421 #define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
422 #define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
423 #define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
427 #define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
428 #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
431 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
432 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
440 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
442 #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
546 #define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
557 #define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
560 #define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
563 #define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
572 #define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
583 #define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
586 #define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
589 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
625 #define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
638 #define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
642 #define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
644 #define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
646 #define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
647 #define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
665 /* Address-Match values and masks (SSB_ADMATCHxxx) */