Lines Matching +full:otp +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
41 #define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
116 #define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */
226 #define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
272 #define SSB_PMU0_PLLCTL2 2
291 #define SSB_PMU1_PLLCTL2 2
311 #define SSB_PMURES_4312_PA_REF_LDO 2
328 #define SSB_PMURES_4325_CBUCK_PWM 2
352 #define SSB_PMURES_4328_BB_SWITCHER_BURST 2
374 #define SSB_PMURES_5354_BB_SWITCHER_BURST 2
395 /** Chip specific Chip-Status register contents. */
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
403 #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
408 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
443 #define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
450 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
458 /* Type 2 Clock control magic field values */
459 #define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
463 #define SSB_CHIPCO_CLK_T2MC_M2BYP 2
470 #define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb))
495 /** Flash-specific control/status values */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
515 #define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2
548 /** OTP **/
550 /* OTP regions */
555 /* OTP regions (Byte offsets from otp size) */
556 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
560 /* Predefined OTP words (Word offset from otp size) */
561 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
562 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
563 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
564 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
568 #define SSB_CHIPCO_OTP_FID_OFF 2
580 * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
601 return (cc->dev != NULL); in ssb_chipco_available()
605 #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
606 #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)