Lines Matching +full:force +full:- +full:m1
1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
115 #define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */
172 #define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
173 #define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
190 #define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
191 #define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
192 #define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
195 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
283 #define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
395 /** Chip specific Chip-Status register contents. */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
434 #define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
445 #define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */
450 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
459 #define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
495 /** Flash-specific control/status values */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
556 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
561 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
562 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
563 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
564 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
580 * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
601 return (cc->dev != NULL); in ssb_chipco_available()
605 #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
606 #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)