Lines Matching +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
174 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
296 #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
321 #define SSB_PMURES_4312_BB_PLL_FILTBYP 12
338 #define SSB_PMURES_4325_LNLDO4_PU 12
362 #define SSB_PMURES_4328_BG_FILTBYP 12
384 #define SSB_PMURES_5354_BG_FILTBYP 12
395 /** Chip specific Chip-Status register contents. */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
450 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
484 #define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */
489 #define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */
495 /** Flash-specific control/status values */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
556 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
561 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
562 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
563 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
564 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
580 * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
601 return (cc->dev != NULL); in ssb_chipco_available()
605 #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
606 #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
634 enum ssb_clkmode mode);