Lines Matching +full:0 +full:x801
62 u8 gpio0; /* GPIO pin 0 */
99 u16 boardflags_lo; /* Board flags (bits 0-15) */
224 #define SSB_DEV_CHIPCOMMON 0x800
225 #define SSB_DEV_ILINE20 0x801
226 #define SSB_DEV_SDRAM 0x803
227 #define SSB_DEV_PCI 0x804
228 #define SSB_DEV_MIPS 0x805
229 #define SSB_DEV_ETHERNET 0x806
230 #define SSB_DEV_V90 0x807
231 #define SSB_DEV_USB11_HOSTDEV 0x808
232 #define SSB_DEV_ADSL 0x809
233 #define SSB_DEV_ILINE100 0x80A
234 #define SSB_DEV_IPSEC 0x80B
235 #define SSB_DEV_PCMCIA 0x80D
236 #define SSB_DEV_INTERNAL_MEM 0x80E
237 #define SSB_DEV_MEMC_SDRAM 0x80F
238 #define SSB_DEV_EXTIF 0x811
239 #define SSB_DEV_80211 0x812
240 #define SSB_DEV_MIPS_3302 0x816
241 #define SSB_DEV_USB11_HOST 0x817
242 #define SSB_DEV_USB11_DEV 0x818
243 #define SSB_DEV_USB20_HOST 0x819
244 #define SSB_DEV_USB20_DEV 0x81A
245 #define SSB_DEV_SDIO_HOST 0x81B
246 #define SSB_DEV_ROBOSWITCH 0x81C
247 #define SSB_DEV_PARA_ATA 0x81D
248 #define SSB_DEV_SATA_XORDMA 0x81E
249 #define SSB_DEV_ETHERNET_GBIT 0x81F
250 #define SSB_DEV_PCIE 0x820
251 #define SSB_DEV_MIMO_PHY 0x821
252 #define SSB_DEV_SRAM_CTRLR 0x822
253 #define SSB_DEV_MINI_MACPHY 0x823
254 #define SSB_DEV_ARM_1176 0x824
255 #define SSB_DEV_ARM_7TDMI 0x825
256 #define SSB_DEV_ARM_CM3 0x82A
259 #define SSB_VENDOR_BROADCOM 0x4243
347 #define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
348 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
349 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
351 #define SSB_BOARD_BCM94301CB 0x0406
352 #define SSB_BOARD_BCM94301MP 0x0407
353 #define SSB_BOARD_BU4309 0x040A
354 #define SSB_BOARD_BCM94309CB 0x040B
355 #define SSB_BOARD_BCM4309MP 0x040C
356 #define SSB_BOARD_BU4306 0x0416
357 #define SSB_BOARD_BCM94306MP 0x0418
358 #define SSB_BOARD_BCM4309G 0x0421
359 #define SSB_BOARD_BCM4306CB 0x0417
360 #define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
361 #define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */
362 #define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */
363 #define SSB_BOARD_BU4704SD 0x042E /* with sdram */
364 #define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */
365 #define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */
366 #define SSB_BOARD_BU4318 0x0447
367 #define SSB_BOARD_CB4318 0x0448
368 #define SSB_BOARD_MPG4318 0x0449
369 #define SSB_BOARD_MP4318 0x044A
370 #define SSB_BOARD_SD4318 0x044B
371 #define SSB_BOARD_BCM94306P 0x044C /* with SiGe */
372 #define SSB_BOARD_BCM94303MP 0x044E
373 #define SSB_BOARD_BCM94306MPM 0x0450
374 #define SSB_BOARD_BCM94306MPL 0x0453
375 #define SSB_BOARD_PC4303 0x0454 /* pcmcia */
376 #define SSB_BOARD_BCM94306MPLNA 0x0457
377 #define SSB_BOARD_BCM94306MPH 0x045B
378 #define SSB_BOARD_BCM94306PCIV 0x045C
379 #define SSB_BOARD_BCM94318MPGH 0x0463
380 #define SSB_BOARD_BU4311 0x0464
381 #define SSB_BOARD_BCM94311MC 0x0465
382 #define SSB_BOARD_BCM94311MCAG 0x0466
384 #define SSB_BOARD_BU4321 0x046B
385 #define SSB_BOARD_BU4321E 0x047C
386 #define SSB_BOARD_MP4321 0x046C
387 #define SSB_BOARD_CB2_4321 0x046D
388 #define SSB_BOARD_CB2_4321_AG 0x0066
389 #define SSB_BOARD_MC4321 0x046E
391 #define SSB_BOARD_BCM94325DEVBU 0x0490
392 #define SSB_BOARD_BCM94325BGABU 0x0491
393 #define SSB_BOARD_BCM94325SDGWB 0x0492
394 #define SSB_BOARD_BCM94325SDGMDL 0x04AA
395 #define SSB_BOARD_BCM94325SDGMDL2 0x04C6
396 #define SSB_BOARD_BCM94325SDGMDL3 0x04C9
397 #define SSB_BOARD_BCM94325SDABGWBA 0x04E1
399 #define SSB_BOARD_BCM94322MC 0x04A4
400 #define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */
401 #define SSB_BOARD_BCM94322HM 0x04B0
402 #define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */
404 #define SSB_BOARD_BU4312 0x048A
405 #define SSB_BOARD_BCM4312MCGSG 0x04B5
409 #define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
509 SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
568 * If no device-specific flags are available, use 0. */
621 #define SSB_DMA_TRANSLATION_MASK 0xC0000000