1 /* SPDX-License-Identifier: GPL-2.0-or-later
36  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
42  * struct spi_statistics - statistics for spi transfers
43  * @syncp:         seqcount to protect members in this struct for per-cpu update
44  *                 on 32-bit systems
46  * @messages:      number of spi-messages handled
95 		u64_stats_update_begin(&__lstats->syncp);		\
96 		u64_stats_add(&__lstats->field, count);			\
97 		u64_stats_update_end(&__lstats->syncp);			\
106 		u64_stats_update_begin(&__lstats->syncp);		\
107 		u64_stats_inc(&__lstats->field);			\
108 		u64_stats_update_end(&__lstats->syncp);			\
113  * struct spi_delay - SPI delay information
131  * struct spi_device - Controller side proxy for an SPI slave device
137  * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
145  *	like eight or 12 bits are common.  In-memory wordsizes are
154  * @controller_data: Board-specific definitions for controller, such as
198 	 * only half-duplex, the wait state detection needs to be implemented
212 #define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
220 	struct spi_delay	word_delay; /* Inter-word delay */
239 	 *  - memory packing (12 bit samples into low bits, others zeroed)
240 	 *  - priority
241 	 *  - chipselect delays
242 	 *  - ...
258 	return (spi && get_device(&spi->dev)) ? spi : NULL;  in spi_dev_get()
264 		put_device(&spi->dev);  in spi_dev_put()
270 	return spi->controller_state;  in spi_get_ctldata()
275 	spi->controller_state = state;  in spi_set_ctldata()
282 	dev_set_drvdata(&spi->dev, data);  in spi_set_drvdata()
287 	return dev_get_drvdata(&spi->dev);  in spi_get_drvdata()
292 	return spi->chip_select[idx];  in spi_get_chipselect()
297 	spi->chip_select[idx] = chipselect;  in spi_set_chipselect()
302 	return spi->cs_gpiod[idx];  in spi_get_csgpiod()
307 	spi->cs_gpiod[idx] = csgpiod;  in spi_set_csgpiod()
322  * struct spi_driver - Host side "protocol" driver
360  * spi_unregister_driver - reverse effect of spi_register_driver
367 		driver_unregister(&sdrv->driver);  in spi_unregister_driver()
377  * module_spi_driver() - Helper macro for registering a SPI driver
389  * struct spi_controller - interface to SPI master or slave controller
392  * @bus_num: board-specific (and often SOC-specific) identifier for a
411  * @devm_allocated: whether the allocation of this struct is devres-managed
430  * @cleanup: frees controller-specific state
440  * @cur_msg: the currently in-flight message
441  * @cur_msg_completion: a completion for the current in-flight message
451  * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip
483  *                  - return 0 if the transfer is finished,
484  *                  - return 1 if the transfer is still in progress. When
489  *                    spi_transfer->error first, before calling
517  * @dummy_rx: dummy receive buffer for full-duplex devices
518  * @dummy_tx: dummy transmit buffer for full-duplex devices
523  *	time snapshot in @spi_transfer->ptp_sts as close as possible to the
524  *	moment in time when @spi_transfer->ptp_sts_word_pre and
525  *	@spi_transfer->ptp_sts_word_post were transmitted.
527  *	close to the driver hand-over as possible.
532  * @defer_optimize_message: set to true if controller cannot pre-optimize messages
554 	 * board-specific. Usually that simplifies to being SoC-specific.
556 	 * and one board's schematics might show it using SPI-2. Software
563 	 * might use board-specific GPIOs.
580 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
581 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
597 	 * The spi-controller has multi chip select capability and can
598 	 * assert/de-assert more than one chip select at once.
602 	/* Flag indicating if the allocation of this struct is devres-managed */
643 	 * configuring CS timing.
646 	 * to configure specific CS timing through spi_set_cs_timing() after
654 	 * + The transfer() method may not sleep; its main role is
656 	 * + For now there's no remove-from-queue operation, or
739 	/* Optimized handlers for SPI memory-like operations. */
779 	return dev_get_drvdata(&ctlr->dev);  in spi_controller_get_devdata()
785 	dev_set_drvdata(&ctlr->dev, data);  in spi_controller_set_devdata()
790 	if (!ctlr || !get_device(&ctlr->dev))  in spi_controller_get()
798 		put_device(&ctlr->dev);  in spi_controller_put()
803 	return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;  in spi_controller_is_target()
882 	return ERR_PTR(-ENODEV);  in acpi_spi_device_alloc()
900  * struct spi_res - SPI resource management structure
903  * @data:    extra data allocated for the specific use-case
905  * This is based on ideas from devres, but focused on life-cycle
914 /*---------------------------------------------------------------------------*/
934  * struct spi_transfer - a read/write buffer pair
935  * @tx_buf: data to be written (DMA-safe memory), or NULL
936  * @rx_buf: data to be read (DMA-safe memory), or NULL
958  * @effective_speed_hz: the effective SCK-speed that was used to
977  *	purposefully (instead of setting to spi_transfer->len - 1) to denote
978  *	that a transfer-level snapshot taken from within the driver may still
982  *	hardware has some sort of assist for retrieving exact transfer timing,
1005  * In-memory data values are always in native CPU byte order, translated
1006  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
1010  * When the word size of the SPI transfer is not a power-of-two multiple
1011  * of eight bits, those in-memory words include extra bits.  In-memory
1012  * words are always seen by protocol drivers as right-justified, so the
1026  * stay selected until the next transfer.  On multi-device SPI busses
1036  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
1042  * Zero-initialize every field you don't set up explicitly, to
1074 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */
1075 #define	SPI_NBITS_DUAL		0x02 /* 2-bit transfer */
1076 #define	SPI_NBITS_QUAD		0x04 /* 4-bit transfer */
1077 #define	SPI_NBITS_OCTAL	0x08 /* 8-bit transfer */
1095  * struct spi_message - one multi-segment SPI transaction
1098  * @pre_optimized: peripheral driver pre-optimized the message
1122  * Zero-initialize every field you don't set up explicitly, to
1145 	 * Some controller drivers (message-at-a-time queue processing)
1147 	 * others (with multi-message pipelines) could need a flag to
1177 	INIT_LIST_HEAD(&m->transfers);  in spi_message_init_no_memset()
1178 	INIT_LIST_HEAD(&m->resources);  in spi_message_init_no_memset()
1190 	list_add_tail(&t->transfer_list, &m->transfers);  in spi_message_add_tail()
1196 	list_del(&t->transfer_list);  in spi_transfer_del()
1202 	return spi_delay_exec(&t->delay, t);  in spi_transfer_delay_exec()
1206  * spi_message_init_with_transfers - Initialize spi_message and append transfers
1241 	spi_message_init_no_memset(&mwt->m);  in spi_message_alloc()
1243 		spi_message_add_tail(&mwt->t[i], &mwt->m);  in spi_message_alloc()
1245 	return &mwt->m;  in spi_message_alloc()
1265 	struct spi_controller *ctlr = spi->controller;  in spi_max_message_size()
1267 	if (!ctlr->max_message_size)  in spi_max_message_size()
1269 	return ctlr->max_message_size(spi);  in spi_max_message_size()
1275 	struct spi_controller *ctlr = spi->controller;  in spi_max_transfer_size()
1279 	if (ctlr->max_transfer_size)  in spi_max_transfer_size()
1280 		tr_max = ctlr->max_transfer_size(spi);  in spi_max_transfer_size()
1287  * spi_is_bpw_supported - Check if bits per word is supported
1298 	u32 bpw_mask = spi->controller->bits_per_word_mask;  in spi_is_bpw_supported()
1307  * spi_controller_xfer_timeout - Compute a suitable timeout value
1320 	return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U);  in spi_controller_xfer_timeout()
1323 /*---------------------------------------------------------------------------*/
1332  * struct spi_replaced_transfers - structure describing the spi_transfer
1341  *                      are to get re-inserted
1343  * @inserted_transfers: array of spi_transfers of array-size @inserted,
1359 /*---------------------------------------------------------------------------*/
1370 /*---------------------------------------------------------------------------*/
1384  * spi_sync_transfer - synchronous SPI data transfer
1408  * spi_write - SPI synchronous write
1431  * spi_read - SPI synchronous read
1459  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1481  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1486  * The number is returned in wire-order, which is at least sometimes
1487  * big-endian.
1506  * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1512  * convert the read 16 bit data word from big-endian to native endianness.
1532 /*---------------------------------------------------------------------------*/
1544  * support for non-static configurations too; enough to handle adding
1545  * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1549  * struct spi_board_info - board-specific template for a SPI device
1552  *	data stored there is driver-specific.
1558  *	from the chip datasheet and board-specific signal quality issues.
1572  * These structures are used in two places.  Their primary role is to
1573  * be stored in tables of board-specific device descriptors, which are
1576  * initializes.  A secondary (and atypical) role is as a parameter to
1619 	 *  - quirks like clock rate mattering when not selected
1665 	return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);  in spi_transfer_is_last()