Lines Matching +full:7 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
39 #define SDW_DP0_INT_TEST_FAIL BIT(0)
40 #define SDW_DP0_INT_PORT_READY BIT(1)
41 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
42 #define SDW_DP0_SDCA_CASCADE BIT(3)
43 /* BIT(4) not allocated in SoundWire specification 1.2 */
44 #define SDW_DP0_INT_IMPDEF1 BIT(5)
45 #define SDW_DP0_INT_IMPDEF2 BIT(6)
46 #define SDW_DP0_INT_IMPDEF3 BIT(7)
55 #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4)
56 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
70 #define SDW_SCP_INT1_PARITY BIT(0)
71 #define SDW_SCP_INT1_BUS_CLASH BIT(1)
72 #define SDW_SCP_INT1_IMPL_DEF BIT(2)
73 #define SDW_SCP_INT1_SCP2_CASCADE BIT(7)
77 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7)
90 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1)
91 #define SDW_SCP_CTRL_FORCE_RESET BIT(7)
94 #define SDW_SCP_STAT_CLK_STP_NF BIT(0)
95 #define SDW_SCP_STAT_HPHY_NOK BIT(5)
96 #define SDW_SCP_STAT_CURR_BANK BIT(6)
99 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0)
100 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2)
101 #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3)
102 #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4)
105 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2)
137 #define SDW_SCP_SDCA_INT_SDCA_0 BIT(0)
138 #define SDW_SCP_SDCA_INT_SDCA_1 BIT(1)
139 #define SDW_SCP_SDCA_INT_SDCA_2 BIT(2)
140 #define SDW_SCP_SDCA_INT_SDCA_3 BIT(3)
141 #define SDW_SCP_SDCA_INT_SDCA_4 BIT(4)
142 #define SDW_SCP_SDCA_INT_SDCA_5 BIT(5)
143 #define SDW_SCP_SDCA_INT_SDCA_6 BIT(6)
144 #define SDW_SCP_SDCA_INT_SDCA_7 BIT(7)
147 #define SDW_SCP_SDCA_INT_SDCA_8 BIT(0)
148 #define SDW_SCP_SDCA_INT_SDCA_9 BIT(1)
149 #define SDW_SCP_SDCA_INT_SDCA_10 BIT(2)
150 #define SDW_SCP_SDCA_INT_SDCA_11 BIT(3)
151 #define SDW_SCP_SDCA_INT_SDCA_12 BIT(4)
152 #define SDW_SCP_SDCA_INT_SDCA_13 BIT(5)
153 #define SDW_SCP_SDCA_INT_SDCA_14 BIT(6)
154 #define SDW_SCP_SDCA_INT_SDCA_15 BIT(7)
157 #define SDW_SCP_SDCA_INT_SDCA_16 BIT(0)
158 #define SDW_SCP_SDCA_INT_SDCA_17 BIT(1)
159 #define SDW_SCP_SDCA_INT_SDCA_18 BIT(2)
160 #define SDW_SCP_SDCA_INT_SDCA_19 BIT(3)
161 #define SDW_SCP_SDCA_INT_SDCA_20 BIT(4)
162 #define SDW_SCP_SDCA_INT_SDCA_21 BIT(5)
163 #define SDW_SCP_SDCA_INT_SDCA_22 BIT(6)
164 #define SDW_SCP_SDCA_INT_SDCA_23 BIT(7)
167 #define SDW_SCP_SDCA_INT_SDCA_24 BIT(0)
168 #define SDW_SCP_SDCA_INT_SDCA_25 BIT(1)
169 #define SDW_SCP_SDCA_INT_SDCA_26 BIT(2)
170 #define SDW_SCP_SDCA_INT_SDCA_27 BIT(3)
171 #define SDW_SCP_SDCA_INT_SDCA_28 BIT(4)
172 #define SDW_SCP_SDCA_INT_SDCA_29 BIT(5)
173 #define SDW_SCP_SDCA_INT_SDCA_30 BIT(6)
174 /* BIT(7) not allocated in SoundWire 1.2 specification */
177 #define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0)
178 #define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1)
179 #define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2)
180 #define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3)
181 #define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4)
182 #define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5)
183 #define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6)
184 #define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7)
187 #define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0)
188 #define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1)
189 #define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2)
190 #define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3)
191 #define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4)
192 #define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5)
193 #define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6)
194 #define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7)
197 #define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0)
198 #define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1)
199 #define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2)
200 #define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3)
201 #define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4)
202 #define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5)
203 #define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6)
204 #define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7)
207 #define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0)
208 #define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1)
209 #define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2)
210 #define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3)
211 #define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4)
212 #define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5)
213 #define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6)
214 /* BIT(7) not allocated in SoundWire 1.2 specification */
226 /* PHY registers - CTRL and STAT are the same address */
238 #define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6)
248 #define SDW_DPN_INT_TEST_FAIL BIT(0)
249 #define SDW_DPN_INT_PORT_READY BIT(1)
250 #define SDW_DPN_INT_IMPDEF1 BIT(5)
251 #define SDW_DPN_INT_IMPDEF2 BIT(6)
252 #define SDW_DPN_INT_IMPDEF3 BIT(7)
261 #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4)
265 #define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0)
294 #define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0)
297 #define SDW_DPN_HCTRL_HSTART GENMASK(7, 4)
305 #define SDW_NUM_CASC_PORT_INTSTAT2 7
316 * v1.2 device - SDCA address mapping
330 * 12:7 Entity[5:0]
335 #define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \
337 (((ent) & BIT(6)) << 15) | \
338 (((ent) & GENMASK(5, 0)) << 7) | \
345 #define SDW_SDCA_CTL_ENT(reg) ((FIELD_GET(BIT(21), (reg)) << 6) | \
346 FIELD_GET(GENMASK(12, 7), (reg)))
352 #define SDW_SDCA_MBQ_CTL(reg) ((reg) | BIT(13))
353 #define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14))
356 #define SDW_SDCA_VALID_CTL(reg) (((reg) & (GENMASK(31, 25) | BIT(18) | BIT(13))) == BIT(30))