Lines Matching +full:multi +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
26 #define SDW_SHIM_LCAP_MLCS_MASK BIT(8)
31 #define SDW_SHIM_LCTL_SPA BIT(0)
33 #define SDW_SHIM_LCTL_CPA BIT(8)
43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1)
45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
46 #define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1)
48 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
50 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
51 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
76 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
81 #define SDW_SHIM_IOCTL_MIF BIT(0)
82 #define SDW_SHIM_IOCTL_CO BIT(1)
83 #define SDW_SHIM_IOCTL_COE BIT(2)
84 #define SDW_SHIM_IOCTL_DO BIT(3)
85 #define SDW_SHIM_IOCTL_DOE BIT(4)
86 #define SDW_SHIM_IOCTL_BKE BIT(5)
87 #define SDW_SHIM_IOCTL_WPDD BIT(6)
88 #define SDW_SHIM_IOCTL_CIBD BIT(8)
89 #define SDW_SHIM_IOCTL_DIBD BIT(9)
94 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
99 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
104 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
105 #define SDW_SHIM_CTMCTL_DODS BIT(1)
117 * ACE2.x definitions for SHIM registers - only accessible when the
126 /* Read-only capabilities */
128 #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
133 #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
134 #define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */
137 /* Read-only PCM Stream Channel Count, y variable is stream */
146 #define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */
148 /* SHIM2 vendor-specific registers */
150 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26)
152 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30)
153 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31)
162 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
165 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
168 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
169 #define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1)
170 #define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2)
171 #define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3)
172 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4)
173 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5)
174 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6)
175 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7)
176 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8)
177 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9)
178 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10)
181 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
182 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1)
183 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
185 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
186 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6)
189 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14)
190 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15)
229 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
231 * @count: link count found with "sdw-master-count" or "sdw-manager-list" property
232 * @link_mask: bit-wise mask listing links enabled by BIOS menu
246 /* Intel clock-stop/pm_runtime quirk definitions */
253 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
257 * reset and re-enumeration will be performed when the bus
259 * in-band wakes.
261 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
265 * (e.g. speaker amplifiers). The clock-stop mode is typically
266 * slightly higher power than when the IP is completely powered-off.
268 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
271 * Require a bus reset (and complete re-enumeration) when exiting
278 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
283 * struct sdw_intel_ctx - context allocated by the controller
288 * @link_mask: bit-wise mask listing SoundWire links reported by the
291 * @ldev: information for each link (controller-specific and kept
315 * struct sdw_intel_res - Soundwire Intel global resource structure,
326 * @link_mask: bit-wise mask listing links selected by the DSP driver
328 * machine-specific quirks are handled in the DSP driver.
335 * @eml_lock: mutex protecting shared registers in the HDaudio multi-link
382 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
386 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
396 * @link_power_up: power-up using chip-specific helpers
397 * @link_power_down: power-down with chip-specific helpers
399 * @shim_wake: enable/disable in-band wake management
402 * @sync_arm: helper for multi-link synchronization
403 * @sync_go_unlocked: helper for multi-link synchronization -
405 * @sync_go: helper for multi-link synchronization
406 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization
407 * and bank switch - shim_lock is assumed to be locked at higher level
446 * and 6 system-unique Device Numbers for wake-capable devices.