Lines Matching +full:0 +full:x7f

10 	PCA9450_TYPE_PCA9450A = 0,
18 	PCA9450_BUCK1 = 0,
33 	PCA9450_DVS_LEVEL_RUN = 0,
38 #define PCA9450_BUCK1_VOLTAGE_NUM	0x80
39 #define PCA9450_BUCK2_VOLTAGE_NUM	0x80
40 #define PCA9450_BUCK3_VOLTAGE_NUM	0x80
41 #define PCA9450_BUCK4_VOLTAGE_NUM	0x80
43 #define PCA9450_BUCK5_VOLTAGE_NUM	0x80
44 #define PCA9450_BUCK6_VOLTAGE_NUM	0x80
46 #define PCA9450_LDO1_VOLTAGE_NUM	0x08
47 #define PCA9450_LDO2_VOLTAGE_NUM	0x08
48 #define PCA9450_LDO3_VOLTAGE_NUM	0x20
49 #define PCA9450_LDO4_VOLTAGE_NUM	0x20
50 #define PCA9450_LDO5_VOLTAGE_NUM	0x10
53 	PCA9450_REG_DEV_ID	    = 0x00,
54 	PCA9450_REG_INT1	    = 0x01,
55 	PCA9450_REG_INT1_MSK	    = 0x02,
56 	PCA9450_REG_STATUS1	    = 0x03,
57 	PCA9450_REG_STATUS2	    = 0x04,
58 	PCA9450_REG_PWRON_STAT	    = 0x05,
59 	PCA9450_REG_SWRST	    = 0x06,
60 	PCA9450_REG_PWRCTRL         = 0x07,
61 	PCA9450_REG_RESET_CTRL      = 0x08,
62 	PCA9450_REG_CONFIG1         = 0x09,
63 	PCA9450_REG_CONFIG2         = 0x0A,
64 	PCA9450_REG_BUCK123_DVS     = 0x0C,
65 	PCA9450_REG_BUCK1OUT_LIMIT  = 0x0D,
66 	PCA9450_REG_BUCK2OUT_LIMIT  = 0x0E,
67 	PCA9450_REG_BUCK3OUT_LIMIT  = 0x0F,
68 	PCA9450_REG_BUCK1CTRL       = 0x10,
69 	PCA9450_REG_BUCK1OUT_DVS0   = 0x11,
70 	PCA9450_REG_BUCK1OUT_DVS1   = 0x12,
71 	PCA9450_REG_BUCK2CTRL       = 0x13,
72 	PCA9450_REG_BUCK2OUT_DVS0   = 0x14,
73 	PCA9450_REG_BUCK2OUT_DVS1   = 0x15,
74 	PCA9450_REG_BUCK3CTRL       = 0x16,
75 	PCA9450_REG_BUCK3OUT_DVS0   = 0x17,
76 	PCA9450_REG_BUCK3OUT_DVS1   = 0x18,
77 	PCA9450_REG_BUCK4CTRL       = 0x19,
78 	PCA9450_REG_BUCK4OUT        = 0x1A,
79 	PCA9450_REG_BUCK5CTRL       = 0x1B,
80 	PCA9450_REG_BUCK5OUT        = 0x1C,
81 	PCA9450_REG_BUCK6CTRL       = 0x1D,
82 	PCA9450_REG_BUCK6OUT        = 0x1E,
83 	PCA9450_REG_LDO_AD_CTRL     = 0x20,
84 	PCA9450_REG_LDO1CTRL        = 0x21,
85 	PCA9450_REG_LDO2CTRL        = 0x22,
86 	PCA9450_REG_LDO3CTRL        = 0x23,
87 	PCA9450_REG_LDO4CTRL        = 0x24,
88 	PCA9450_REG_LDO5CTRL_L      = 0x25,
89 	PCA9450_REG_LDO5CTRL_H      = 0x26,
90 	PCA9450_REG_LOADSW_CTRL     = 0x2A,
91 	PCA9450_REG_VRFLT1_STS      = 0x2B,
92 	PCA9450_REG_VRFLT2_STS      = 0x2C,
93 	PCA9450_REG_VRFLT1_MASK     = 0x2D,
94 	PCA9450_REG_VRFLT2_MASK     = 0x2E,
95 	PCA9450_MAX_REGISTER	    = 0x2F,
99 #define BUCK_ENMODE_OFF			0x00
100 #define BUCK_ENMODE_ONREQ		0x01
101 #define BUCK_ENMODE_ONREQ_STBYREQ	0x02
102 #define BUCK_ENMODE_ON			0x03
105 #define BUCK1_RAMP_MASK			0xC0
106 #define BUCK1_RAMP_25MV			0x0
107 #define BUCK1_RAMP_12P5MV		0x1
108 #define BUCK1_RAMP_6P25MV		0x2
109 #define BUCK1_RAMP_3P125MV		0x3
110 #define BUCK1_DVS_CTRL			0x10
111 #define BUCK1_AD			0x08
112 #define BUCK1_FPWM			0x04
113 #define BUCK1_ENMODE_MASK		0x03
116 #define BUCK2_RAMP_MASK			0xC0
117 #define BUCK2_RAMP_25MV			0x0
118 #define BUCK2_RAMP_12P5MV		0x1
119 #define BUCK2_RAMP_6P25MV		0x2
120 #define BUCK2_RAMP_3P125MV		0x3
121 #define BUCK2_DVS_CTRL			0x10
122 #define BUCK2_AD			0x08
123 #define BUCK2_FPWM			0x04
124 #define BUCK2_ENMODE_MASK		0x03
127 #define BUCK3_RAMP_MASK			0xC0
128 #define BUCK3_RAMP_25MV			0x0
129 #define BUCK3_RAMP_12P5MV		0x1
130 #define BUCK3_RAMP_6P25MV		0x2
131 #define BUCK3_RAMP_3P125MV		0x3
132 #define BUCK3_DVS_CTRL			0x10
133 #define BUCK3_AD			0x08
134 #define BUCK3_FPWM			0x04
135 #define BUCK3_ENMODE_MASK		0x03
138 #define BUCK4_AD			0x08
139 #define BUCK4_FPWM			0x04
140 #define BUCK4_ENMODE_MASK		0x03
143 #define BUCK5_AD			0x08
144 #define BUCK5_FPWM			0x04
145 #define BUCK5_ENMODE_MASK		0x03
148 #define BUCK6_AD			0x08
149 #define BUCK6_FPWM			0x04
150 #define BUCK6_ENMODE_MASK		0x03
153 #define BUCK123_PRESET_EN		0x80
156 #define BUCK1OUT_DVS0_MASK		0x7F
157 #define BUCK1OUT_DVS0_DEFAULT		0x14
160 #define BUCK1OUT_DVS1_MASK		0x7F
161 #define BUCK1OUT_DVS1_DEFAULT		0x14
164 #define BUCK2OUT_DVS0_MASK		0x7F
165 #define BUCK2OUT_DVS0_DEFAULT		0x14
168 #define BUCK2OUT_DVS1_MASK		0x7F
169 #define BUCK2OUT_DVS1_DEFAULT		0x14
172 #define BUCK3OUT_DVS0_MASK		0x7F
173 #define BUCK3OUT_DVS0_DEFAULT		0x14
176 #define BUCK3OUT_DVS1_MASK		0x7F
177 #define BUCK3OUT_DVS1_DEFAULT		0x14
180 #define BUCK4OUT_MASK			0x7F
181 #define BUCK4OUT_DEFAULT		0x6C
184 #define BUCK5OUT_MASK			0x7F
185 #define BUCK5OUT_DEFAULT		0x30
188 #define BUCK6OUT_MASK			0x7F
189 #define BUCK6OUT_DEFAULT		0x14
192 #define LDO1_EN_MASK			0xC0
193 #define LDO1OUT_MASK			0x07
196 #define LDO2_EN_MASK			0xC0
197 #define LDO2OUT_MASK			0x07
200 #define LDO3_EN_MASK			0xC0
201 #define LDO3OUT_MASK			0x1F
204 #define LDO4_EN_MASK			0xC0
205 #define LDO4OUT_MASK			0x1F
208 #define LDO5L_EN_MASK			0xC0
209 #define LDO5LOUT_MASK			0x0F
211 #define LDO5H_EN_MASK			0xC0
212 #define LDO5HOUT_MASK			0x0F
215 #define IRQ_PWRON			0x80
216 #define IRQ_WDOGB			0x40
217 #define IRQ_RSVD			0x20
218 #define IRQ_VR_FLT1			0x10
219 #define IRQ_VR_FLT2			0x08
220 #define IRQ_LOWVSYS			0x04
221 #define IRQ_THERM_105			0x02
222 #define IRQ_THERM_125			0x01
225 #define WDOG_B_CFG_MASK			0xC0
226 #define WDOG_B_CFG_NONE			0x00
227 #define WDOG_B_CFG_WARM			0x40
228 #define WDOG_B_CFG_COLD_LDO12		0x80
229 #define WDOG_B_CFG_COLD			0xC0
232 #define I2C_LT_MASK			0x03
233 #define I2C_LT_FORCE_DISABLE		0x00
234 #define I2C_LT_ON_STANDBY_RUN		0x01
235 #define I2C_LT_ON_RUN			0x02
236 #define I2C_LT_FORCE_ENABLE		0x03