Lines Matching +full:tx +full:- +full:frame +full:- +full:sync +full:- +full:delay +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
17 #include <linux/bits.h>
31 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
42 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
48 /* Common PXA2xx bits first */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
112 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
113 #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
129 /* Extra bits in PXA255, PXA26x and PXA27x SSP ports */
130 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
131 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
135 #define SSCR1_IFS BIT(16) /* Invert Frame Signal */
137 #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
142 #define SSCR1_SFRMDIR BIT(24) /* Frame Direction */
152 #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
159 #define SSPSP_SFRMP BIT(2) /* Serial Frame Polarity */
161 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
163 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
164 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
166 #define SSPSP_FSRT BIT(25) /* Frame Sync Relative Timing */
197 #define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */
199 #define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */
202 #define SSITF 0x44 /* TX FIFO trigger level */
203 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
207 #define SSIRF_RxThresh(x) ((x) - 1)
253 * pxa_ssp_write_reg - Write to a SSP register
261 __raw_writel(val, dev->mmio_base + reg); in pxa_ssp_write_reg()
265 * pxa_ssp_read_reg - Read from a SSP register
272 return __raw_readl(dev->mmio_base + reg); in pxa_ssp_read_reg()