Lines Matching +full:platform +full:- +full:pll

1 /* SPDX-License-Identifier: GPL-2.0 */
10  * enum si5351_pll_src - Si5351 pll clock source
12  * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13  * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22  * enum si5351_multisynth_src - Si5351 multisynth clock source
34  * enum si5351_clkout_src - Si5351 clock output clock source
51  * enum si5351_drive_strength - Si5351 clock output drive strength
67  * enum si5351_disable_state - Si5351 clock output disable state
84  * struct si5351_clkout_config - Si5351 clock output configuration
88  * @pll_master: if true, clkout can also change pll rate
89  * @pll_reset: if true, clkout can reset its pll
104  * struct si5351_platform_data - Platform data for the Si5351 clock driver
107  * @pll_src: array of pll source clock setting