Lines Matching +full:oe +full:- +full:extra +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
51 /* OE signals timings corresponding to GPMC_CONFIG4 */
52 u32 oe_on; /* OE assertion time */
53 u32 oe_off; /* OE deassertion time */
54 u32 oe_aad_mux_on; /* OE assertion time for AAD */
55 u32 oe_aad_mux_off; /* OE deassertion time for AAD */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
90 u32 t_oeasu; /* address setup to OE valid */
93 u32 t_oe; /* access time from OE assertion */
98 u32 t_oez; /* OE deassertion to high Z */
105 u32 t_bacc; /* burst access valid clock to output delay */
113 u32 t_ce_avd; /* CS on to ADV on delay */
120 u8 cyc_oe; /* access time from OE assertion in cycles */
124 /* extra delays */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
158 u32 wait_pin; /* wait-pin to be used */