Lines Matching +full:adv +full:- +full:extra +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 /* ADV signal timings corresponding to GPMC_CONFIG3 */
43 u32 adv_aad_mux_on; /* ADV assertion time for AAD */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
79 u32 t_avdasu; /* address setup to ADV valid */
87 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
91 u32 t_aa; /* access time from ADV assertion */
105 u32 t_bacc; /* burst access valid clock to output delay */
107 u32 t_avds; /* ADV setup time to clk */
108 u32 t_avdh; /* ADV hold time from clk */
113 u32 t_ce_avd; /* CS on to ADV on delay */
124 /* extra delays */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
158 u32 wait_pin; /* wait-pin to be used */