Lines Matching +full:nand +full:- +full:int +full:- +full:base
1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* NAND OP_CMDs */
172 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
196 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
198 /* Returns the NAND register physical address */
199 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
203 ((chip)->reg_read_dma + \
204 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
232 * NAND transfers.
233 * @bam_ce - the array of BAM command elements
234 * @cmd_sgl - sgl for NAND BAM command pipe
235 * @data_sgl - sgl for NAND BAM consumer/producer pipe
236 * @last_data_desc - last DMA desc in data channel (tx/rx).
237 * @last_cmd_desc - last DMA desc in command channel.
238 * @txn_done - completion for NAND transfer.
239 * @bam_ce_pos - the index in bam_ce which is available for next sgl
240 * @bam_ce_start - the index in bam_ce which marks the start position ce
243 * @cmd_sgl_pos - current index in command sgl.
244 * @cmd_sgl_start - start index in command sgl.
245 * @tx_sgl_pos - current index in data sgl for tx.
246 * @tx_sgl_start - start index in data sgl for tx.
247 * @rx_sgl_pos - current index in data sgl for rx.
248 * @rx_sgl_start - start index in data sgl for rx.
271 * This data type corresponds to the nand dma descriptor
272 * @dma_desc - low level DMA engine descriptor
273 * @list - list for desc_info
275 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
277 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
278 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
279 * @dir - DMA transfer direction
289 int sgl_cnt;
334 * NAND controller data struct
338 * @base: MMIO base
347 * @props: properties of current NAND controller,
350 * @controller: base controller structure
365 * @base_phys: physical base address of controller registers
366 * @base_dma: dma base address of controller registers
369 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
372 * from all connected NAND devices pagesize
384 void __iomem *base; member
408 unsigned int cmd_crci;
409 unsigned int data_crci;
422 int buf_size;
423 int buf_count;
424 int buf_start;
425 unsigned int max_cwperpage;
427 int reg_read_pos;
434 * This data type corresponds to the NAND controller properties which varies
435 * among different NAND controllers.
436 * @ecc_modes - ecc mode for NAND
437 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
438 * @supports_bam - whether NAND controller is using BAM
439 * @nandc_part_of_qpic - whether NAND controller is part of qpic IP
440 * @qpic_version2 - flag to indicate QPIC IP version 2
441 * @use_codeword_fixup - whether NAND has different layout for boot partitions
457 int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
459 int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
460 int reg_off, const void *vaddr, int size, unsigned int flags);
461 int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
462 const void *vaddr, int size, unsigned int flags);
463 int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off,
464 const void *vaddr, int size, bool flow_control);
465 int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs,
466 unsigned int flags);
467 int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, int first,
468 int num_regs, unsigned int flags);
469 int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
470 int size, unsigned int flags);
471 int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
472 int size, unsigned int flags);
473 int qcom_submit_descs(struct qcom_nand_controller *nandc);
476 int qcom_nandc_alloc(struct qcom_nand_controller *nandc);