Lines Matching +full:1 +full:ac
30 /* class 1 */
32 #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
34 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
36 #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
37 #define MMC_SWITCH 6 /* ac [31:0] See below R1b */
38 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
40 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
41 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
43 #define MMC_STOP_TRANSMISSION 12 /* ac R1b */
44 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
46 #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
52 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
69 #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
70 #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
74 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
75 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
76 #define MMC_ERASE 38 /* ac R1b */
79 #define MMC_FAST_IO 39 /* ac <Complex> R4 */
86 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
90 #define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
91 #define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
94 #define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
134 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
135 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
136 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
137 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
138 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
139 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
140 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
141 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
142 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
143 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
144 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
145 #define R1_CC_ERROR (1 << 20) /* erx, c */
146 #define R1_ERROR (1 << 19) /* erx, c */
147 #define R1_UNDERRUN (1 << 18) /* ex, c */
148 #define R1_OVERRUN (1 << 17) /* ex, c */
149 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
150 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
151 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
152 #define R1_ERASE_RESET (1 << 13) /* sr, c */
155 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
156 #define R1_SWITCH_ERROR (1 << 7) /* sx, c */
157 #define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
158 #define R1_APP_CMD (1 << 5) /* sr, c */
161 #define R1_STATE_READY 1
184 #define R1_SPI_IDLE (1 << 0)
185 #define R1_SPI_ERASE_RESET (1 << 1)
186 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
187 #define R1_SPI_COM_CRC (1 << 3)
188 #define R1_SPI_ERASE_SEQ (1 << 4)
189 #define R1_SPI_ADDRESS (1 << 5)
190 #define R1_SPI_PARAMETER (1 << 6)
192 #define R2_SPI_CARD_LOCKED (1 << 8)
193 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
195 #define R2_SPI_ERROR (1 << 10)
196 #define R2_SPI_CC_ERROR (1 << 11)
197 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
198 #define R2_SPI_WP_VIOLATION (1 << 13)
199 #define R2_SPI_ERASE_PARAM (1 << 14)
200 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
211 #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
212 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
214 #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
216 #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
218 #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
220 #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
222 #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
224 #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
226 #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
228 #define CCC_APP_SPEC (1<<8) /* (8) Application specific */
230 #define CCC_IO_MODE (1<<9) /* (9) I/O mode */
232 #define CCC_SWITCH (1<<10) /* (10) High speed switch */
242 #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
247 #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
329 #define EXT_CSD_WR_REL_PARAM_EN (1<<2)
330 #define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4)
345 #define EXT_CSD_CMD_SET_NORMAL (1<<0)
346 #define EXT_CSD_CMD_SET_SECURE (1<<1)
347 #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
349 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
350 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
353 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
355 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
359 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
360 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
364 #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
365 #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
368 #define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
370 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
371 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
378 #define EXT_CSD_TIMING_HS 1 /* High speed */
389 #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
392 #define EXT_CSD_POWER_ON 1
405 #define EXT_CSD_DYNCAP_NEEDED BIT(1)
430 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
431 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
446 #define mmc_driver_type_mask(n) (1 << (n))