Lines Matching +full:0 +full:x6001
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
79 MLX5_SQP_SMI = 0,
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PCAM = 0x507f,
134 MLX5_REG_NODE_DESC = 0x6001,
135 MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 MLX5_REG_MTCAP = 0x9009,
137 MLX5_REG_MTMP = 0x900A,
138 MLX5_REG_MCIA = 0x9014,
139 MLX5_REG_MFRL = 0x9028,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MRTC = 0x902d,
142 MLX5_REG_MTRC_CAP = 0x9040,
143 MLX5_REG_MTRC_CONF = 0x9041,
144 MLX5_REG_MTRC_STDB = 0x9042,
145 MLX5_REG_MTRC_CTRL = 0x9043,
146 MLX5_REG_MPEIN = 0x9050,
147 MLX5_REG_MPCNT = 0x9051,
148 MLX5_REG_MTPPS = 0x9053,
149 MLX5_REG_MTPPSE = 0x9054,
150 MLX5_REG_MTUTC = 0x9055,
151 MLX5_REG_MPEGC = 0x9056,
152 MLX5_REG_MPIR = 0x9059,
153 MLX5_REG_MCQS = 0x9060,
154 MLX5_REG_MCQI = 0x9061,
155 MLX5_REG_MCC = 0x9062,
156 MLX5_REG_MCDA = 0x9063,
157 MLX5_REG_MCAM = 0x907f,
158 MLX5_REG_MSECQ = 0x9155,
159 MLX5_REG_MSEES = 0x9156,
160 MLX5_REG_MIRC = 0x9162,
161 MLX5_REG_MTPTM = 0x9180,
162 MLX5_REG_MTCTR = 0x9181,
163 MLX5_REG_MRTCQ = 0x9182,
164 MLX5_REG_SBCAM = 0xB01F,
165 MLX5_REG_RESOURCE_DUMP = 0xC000,
166 MLX5_REG_NIC_CAP = 0xC00D,
167 MLX5_REG_DTOR = 0xC00E,
168 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
177 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
178 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
182 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
189 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
202 MLX5_POLICY_DOWN = 0,
205 MLX5_POLICY_INVALID = 0xffffffff
227 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
524 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
630 MLX5_INTERFACE_STATE_UP = BIT(0),
640 MLX5_PFAULT_REQUESTOR = 1 << 0,
719 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
828 MLX5_PTYS_IB = 1 << 0,
900 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
906 return ioread32be(&dev->iseg->fw_rev) & 0xffff; in fw_rev_maj()
916 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; in fw_rev_sub()
921 return key & 0xffffff00u; in mlx5_base_mkey()
947 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); in mlx5_init_fbc()
1125 return mkey & 0xff; in mlx5_mkey_variant()
1168 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1195 MLX5_PCI_DEV_IS_VF = 1 << 0,
1256 return 0; in mlx5_get_gid_table_len()