Lines Matching +full:max +full:- +full:cur
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
51 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
56 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf…
57 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1…
58 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
255 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
499 * Max wqe size for rdma read is 512 bytes, so this
501 * - ctrl segment (16 bytes)
502 * - rdma segment (16 bytes)
503 * - scatter elements (16 bytes each)
505 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
909 return (cqe->op_own >> 2) & 0x3; in mlx5_get_cqe_format()
914 return cqe->op_own >> 4; in get_cqe_opcode()
925 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1; in get_cqe_lro_tcppsh()
930 return (cqe->l4_l3_hdr_type >> 4) & 0x7; in get_cqe_l4_hdr_type()
935 return cqe->tls_outer_l3_tunneled & 0x1; in cqe_is_tunneled()
940 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; in get_cqe_tls_offload()
945 return cqe->l4_l3_hdr_type & 0x1; in cqe_has_vlan()
952 hi = be32_to_cpu(cqe->timestamp_h); in get_cqe_ts()
953 lo = be32_to_cpu(cqe->timestamp_l); in get_cqe_ts()
960 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; in get_cqe_flow_tag()
976 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; in mpwrq_get_cqe_byte_cnt()
978 return be16_to_cpu(bc->byte_cnt); in mpwrq_get_cqe_byte_cnt()
983 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); in mpwrq_get_cqe_bc_consumed_strides()
988 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; in mpwrq_get_cqe_consumed_strides()
995 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; in mpwrq_is_filler_cqe()
997 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); in mpwrq_is_filler_cqe()
1002 return be16_to_cpu(cqe->wqe_counter); in mpwrq_get_cqe_stride_index()
1015 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
1024 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
1097 /* This is a two bit field occupying bits 31-30.
1286 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1289 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1292 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1295 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1298 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1301 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1305 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1309 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1312 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1315 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1318 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1321 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1324 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1327 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1349 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1368 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1372 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1376 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1380 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1384 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1393 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1396 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1398 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1400 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1404 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1407 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1410 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1413 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1416 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1419 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1423 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1427 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
1431 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1434 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1437 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1440 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1443 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1446 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1449 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1452 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1455 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1459 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1463 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1466 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1469 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1472 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1475 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)