1224 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1253 	/* NUM OF CAP Types */
1285 #define MLX5_CAP_GEN(mdev, cap) \  argument
1286 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1288 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1289 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1291 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1292 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1294 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1295 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1297 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1298 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1300 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1301 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1303 #define MLX5_CAP_ETH(mdev, cap) \  argument
1305 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1307 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1309 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1311 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1312 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1314 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1315 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1317 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1318 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1320 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1321 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1323 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1324 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1326 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1327 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1329 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1330 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1332 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1333 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1335 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1336 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1338 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1339 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1341 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1342 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1344 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1345 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1347 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1349 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1351 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1352 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1354 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1355 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1357 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1358 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1360 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1361 	MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1363 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1364 		MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1366 #define MLX5_CAP_ESW(mdev, cap) \  argument
1368 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1370 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1372 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1374 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1376 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1378 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1380 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1382 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1384 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1386 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1387 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1389 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1390 	MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1392 #define MLX5_CAP_ODP(mdev, cap)\  argument
1393 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1395 #define MLX5_CAP_ODP_SCHEME(mdev, cap)                                \  argument
1399 			  memory_page_fault_scheme_cap.cap) :         \
1401 			  transport_page_fault_scheme_cap.cap))
1403 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1404 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1406 #define MLX5_CAP_QOS(mdev, cap)\  argument
1407 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1409 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1410 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1439 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1440 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1442 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1443 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1445 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1446 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1448 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1449 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1451 #define MLX5_CAP_TLS(mdev, cap) \  argument
1452 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1454 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1455 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1457 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1459 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1461 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1463 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1465 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1466 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1468 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1469 	MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1471 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1472 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1474 #define MLX5_CAP_SHAMPO(mdev, cap) \  argument
1475 	MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)