Lines Matching +full:0 +full:x409
27 /* Registers for page 0 */
28 #define TPS6594_REG_DEV_REV 0x01
30 #define TPS6594_REG_NVM_CODE_1 0x02
31 #define TPS6594_REG_NVM_CODE_2 0x03
33 #define TPS6594_REG_BUCKX_CTRL(buck_inst) (0x04 + ((buck_inst) << 1))
34 #define TPS6594_REG_BUCKX_CONF(buck_inst) (0x05 + ((buck_inst) << 1))
35 #define TPS6594_REG_BUCKX_VOUT_1(buck_inst) (0x0e + ((buck_inst) << 1))
36 #define TPS6594_REG_BUCKX_VOUT_2(buck_inst) (0x0f + ((buck_inst) << 1))
37 #define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst) (0x18 + (buck_inst))
39 #define TPS6594_REG_LDOX_CTRL(ldo_inst) (0x1d + (ldo_inst))
40 #define TPS6594_REG_LDORTC_CTRL 0x22
41 #define TPS6594_REG_LDOX_VOUT(ldo_inst) (0x23 + (ldo_inst))
42 #define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst) (0x27 + (ldo_inst))
44 #define TPS6594_REG_VCCA_VMON_CTRL 0x2b
45 #define TPS6594_REG_VCCA_PG_WINDOW 0x2c
46 #define TPS6594_REG_VMON1_PG_WINDOW 0x2d
47 #define TPS6594_REG_VMON1_PG_LEVEL 0x2e
48 #define TPS6594_REG_VMON2_PG_WINDOW 0x2f
49 #define TPS6594_REG_VMON2_PG_LEVEL 0x30
51 #define TPS6594_REG_GPIOX_CONF(gpio_inst) (0x31 + (gpio_inst))
52 #define TPS6594_REG_NPWRON_CONF 0x3c
53 #define TPS6594_REG_GPIO_OUT_1 0x3d
54 #define TPS6594_REG_GPIO_OUT_2 0x3e
55 #define TPS6594_REG_GPIO_IN_1 0x3f
56 #define TPS6594_REG_GPIO_IN_2 0x40
60 #define TPS6594_REG_RAIL_SEL_1 0x41
61 #define TPS6594_REG_RAIL_SEL_2 0x42
62 #define TPS6594_REG_RAIL_SEL_3 0x43
64 #define TPS6594_REG_FSM_TRIG_SEL_1 0x44
65 #define TPS6594_REG_FSM_TRIG_SEL_2 0x45
66 #define TPS6594_REG_FSM_TRIG_MASK_1 0x46
67 #define TPS6594_REG_FSM_TRIG_MASK_2 0x47
68 #define TPS6594_REG_FSM_TRIG_MASK_3 0x48
70 #define TPS6594_REG_MASK_BUCK1_2 0x49
71 #define TPS65224_REG_MASK_BUCKS 0x49
72 #define TPS6594_REG_MASK_BUCK3_4 0x4a
73 #define TPS6594_REG_MASK_BUCK5 0x4b
74 #define TPS6594_REG_MASK_LDO1_2 0x4c
75 #define TPS65224_REG_MASK_LDOS 0x4c
76 #define TPS6594_REG_MASK_LDO3_4 0x4d
77 #define TPS6594_REG_MASK_VMON 0x4e
78 #define TPS6594_REG_MASK_GPIO_FALL 0x4f
79 #define TPS6594_REG_MASK_GPIO_RISE 0x50
80 #define TPS6594_REG_MASK_GPIO9_11 0x51
81 #define TPS6594_REG_MASK_STARTUP 0x52
82 #define TPS6594_REG_MASK_MISC 0x53
83 #define TPS6594_REG_MASK_MODERATE_ERR 0x54
84 #define TPS6594_REG_MASK_FSM_ERR 0x56
85 #define TPS6594_REG_MASK_COMM_ERR 0x57
86 #define TPS6594_REG_MASK_READBACK_ERR 0x58
87 #define TPS6594_REG_MASK_ESM 0x59
89 #define TPS6594_REG_INT_TOP 0x5a
90 #define TPS6594_REG_INT_BUCK 0x5b
91 #define TPS6594_REG_INT_BUCK1_2 0x5c
92 #define TPS6594_REG_INT_BUCK3_4 0x5d
93 #define TPS6594_REG_INT_BUCK5 0x5e
94 #define TPS6594_REG_INT_LDO_VMON 0x5f
95 #define TPS6594_REG_INT_LDO1_2 0x60
96 #define TPS6594_REG_INT_LDO3_4 0x61
97 #define TPS6594_REG_INT_VMON 0x62
98 #define TPS6594_REG_INT_GPIO 0x63
99 #define TPS6594_REG_INT_GPIO1_8 0x64
100 #define TPS6594_REG_INT_STARTUP 0x65
101 #define TPS6594_REG_INT_MISC 0x66
102 #define TPS6594_REG_INT_MODERATE_ERR 0x67
103 #define TPS6594_REG_INT_SEVERE_ERR 0x68
104 #define TPS6594_REG_INT_FSM_ERR 0x69
105 #define TPS6594_REG_INT_COMM_ERR 0x6a
106 #define TPS6594_REG_INT_READBACK_ERR 0x6b
107 #define TPS6594_REG_INT_ESM 0x6c
109 #define TPS6594_REG_STAT_BUCK1_2 0x6d
110 #define TPS6594_REG_STAT_BUCK3_4 0x6e
111 #define TPS6594_REG_STAT_BUCK5 0x6f
112 #define TPS6594_REG_STAT_LDO1_2 0x70
113 #define TPS6594_REG_STAT_LDO3_4 0x71
114 #define TPS6594_REG_STAT_VMON 0x72
115 #define TPS6594_REG_STAT_STARTUP 0x73
116 #define TPS6594_REG_STAT_MISC 0x74
117 #define TPS6594_REG_STAT_MODERATE_ERR 0x75
118 #define TPS6594_REG_STAT_SEVERE_ERR 0x76
119 #define TPS6594_REG_STAT_READBACK_ERR 0x77
121 #define TPS6594_REG_PGOOD_SEL_1 0x78
122 #define TPS6594_REG_PGOOD_SEL_2 0x79
123 #define TPS6594_REG_PGOOD_SEL_3 0x7a
124 #define TPS6594_REG_PGOOD_SEL_4 0x7b
126 #define TPS6594_REG_PLL_CTRL 0x7c
128 #define TPS6594_REG_CONFIG_1 0x7d
129 #define TPS6594_REG_CONFIG_2 0x7e
131 #define TPS6594_REG_ENABLE_DRV_REG 0x80
133 #define TPS6594_REG_MISC_CTRL 0x81
135 #define TPS6594_REG_ENABLE_DRV_STAT 0x82
137 #define TPS6594_REG_RECOV_CNT_REG_1 0x83
138 #define TPS6594_REG_RECOV_CNT_REG_2 0x84
140 #define TPS6594_REG_FSM_I2C_TRIGGERS 0x85
141 #define TPS6594_REG_FSM_NSLEEP_TRIGGERS 0x86
143 #define TPS6594_REG_BUCK_RESET_REG 0x87
145 #define TPS6594_REG_SPREAD_SPECTRUM_1 0x88
147 #define TPS6594_REG_FREQ_SEL 0x8a
149 #define TPS6594_REG_FSM_STEP_SIZE 0x8b
151 #define TPS6594_REG_LDO_RV_TIMEOUT_REG_1 0x8c
152 #define TPS6594_REG_LDO_RV_TIMEOUT_REG_2 0x8d
154 #define TPS6594_REG_USER_SPARE_REGS 0x8e
156 #define TPS6594_REG_ESM_MCU_START_REG 0x8f
157 #define TPS6594_REG_ESM_MCU_DELAY1_REG 0x90
158 #define TPS6594_REG_ESM_MCU_DELAY2_REG 0x91
159 #define TPS6594_REG_ESM_MCU_MODE_CFG 0x92
160 #define TPS6594_REG_ESM_MCU_HMAX_REG 0x93
161 #define TPS6594_REG_ESM_MCU_HMIN_REG 0x94
162 #define TPS6594_REG_ESM_MCU_LMAX_REG 0x95
163 #define TPS6594_REG_ESM_MCU_LMIN_REG 0x96
164 #define TPS6594_REG_ESM_MCU_ERR_CNT_REG 0x97
165 #define TPS6594_REG_ESM_SOC_START_REG 0x98
166 #define TPS6594_REG_ESM_SOC_DELAY1_REG 0x99
167 #define TPS6594_REG_ESM_SOC_DELAY2_REG 0x9a
168 #define TPS6594_REG_ESM_SOC_MODE_CFG 0x9b
169 #define TPS6594_REG_ESM_SOC_HMAX_REG 0x9c
170 #define TPS6594_REG_ESM_SOC_HMIN_REG 0x9d
171 #define TPS6594_REG_ESM_SOC_LMAX_REG 0x9e
172 #define TPS6594_REG_ESM_SOC_LMIN_REG 0x9f
173 #define TPS6594_REG_ESM_SOC_ERR_CNT_REG 0xa0
175 #define TPS6594_REG_REGISTER_LOCK 0xa1
177 #define TPS65224_REG_SRAM_ACCESS_1 0xa2
178 #define TPS65224_REG_SRAM_ACCESS_2 0xa3
179 #define TPS65224_REG_SRAM_ADDR_CTRL 0xa4
180 #define TPS65224_REG_RECOV_CNT_PFSM_INCR 0xa5
181 #define TPS6594_REG_MANUFACTURING_VER 0xa6
183 #define TPS6594_REG_CUSTOMER_NVM_ID_REG 0xa7
185 #define TPS6594_REG_VMON_CONF_REG 0xa8
187 #define TPS6594_REG_SOFT_REBOOT_REG 0xab
189 #define TPS65224_REG_ADC_CTRL 0xac
190 #define TPS65224_REG_ADC_RESULT_REG_1 0xad
191 #define TPS65224_REG_ADC_RESULT_REG_2 0xae
192 #define TPS6594_REG_RTC_SECONDS 0xb5
193 #define TPS6594_REG_RTC_MINUTES 0xb6
194 #define TPS6594_REG_RTC_HOURS 0xb7
195 #define TPS6594_REG_RTC_DAYS 0xb8
196 #define TPS6594_REG_RTC_MONTHS 0xb9
197 #define TPS6594_REG_RTC_YEARS 0xba
198 #define TPS6594_REG_RTC_WEEKS 0xbb
200 #define TPS6594_REG_ALARM_SECONDS 0xbc
201 #define TPS6594_REG_ALARM_MINUTES 0xbd
202 #define TPS6594_REG_ALARM_HOURS 0xbe
203 #define TPS6594_REG_ALARM_DAYS 0xbf
204 #define TPS6594_REG_ALARM_MONTHS 0xc0
205 #define TPS6594_REG_ALARM_YEARS 0xc1
207 #define TPS6594_REG_RTC_CTRL_1 0xc2
208 #define TPS6594_REG_RTC_CTRL_2 0xc3
209 #define TPS65224_REG_STARTUP_CTRL 0xc3
210 #define TPS6594_REG_RTC_STATUS 0xc4
211 #define TPS6594_REG_RTC_INTERRUPTS 0xc5
212 #define TPS6594_REG_RTC_COMP_LSB 0xc6
213 #define TPS6594_REG_RTC_COMP_MSB 0xc7
214 #define TPS6594_REG_RTC_RESET_STATUS 0xc8
216 #define TPS6594_REG_SCRATCH_PAD_REG_1 0xc9
217 #define TPS6594_REG_SCRATCH_PAD_REG_2 0xca
218 #define TPS6594_REG_SCRATCH_PAD_REG_3 0xcb
219 #define TPS6594_REG_SCRATCH_PAD_REG_4 0xcc
221 #define TPS6594_REG_PFSM_DELAY_REG_1 0xcd
222 #define TPS6594_REG_PFSM_DELAY_REG_2 0xce
223 #define TPS6594_REG_PFSM_DELAY_REG_3 0xcf
224 #define TPS6594_REG_PFSM_DELAY_REG_4 0xd0
225 #define TPS65224_REG_ADC_GAIN_COMP_REG 0xd0
226 #define TPS65224_REG_CRC_CALC_CONTROL 0xef
227 #define TPS65224_REG_REGMAP_USER_CRC_LOW 0xf0
228 #define TPS65224_REG_REGMAP_USER_CRC_HIGH 0xf1
231 #define TPS6594_REG_SERIAL_IF_CONFIG 0x11a
232 #define TPS6594_REG_I2C1_ID 0x122
233 #define TPS6594_REG_I2C2_ID 0x123
236 #define TPS6594_REG_WD_ANSWER_REG 0x401
237 #define TPS6594_REG_WD_QUESTION_ANSW_CNT 0x402
238 #define TPS6594_REG_WD_WIN1_CFG 0x403
239 #define TPS6594_REG_WD_WIN2_CFG 0x404
240 #define TPS6594_REG_WD_LONGWIN_CFG 0x405
241 #define TPS6594_REG_WD_MODE_REG 0x406
242 #define TPS6594_REG_WD_QA_CFG 0x407
243 #define TPS6594_REG_WD_ERR_STATUS 0x408
244 #define TPS6594_REG_WD_THR_CFG 0x409
245 #define TPS6594_REG_DWD_FAIL_CNT_REG 0x40a
248 #define TPS6594_BIT_BUCK_EN BIT(0)
257 #define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)
261 #define TPS65224_MASK_BUCK_SLEW_RATE GENMASK(1, 0)
264 #define TPS6594_MASK_BUCK_OV_THR GENMASK(2, 0)
268 #define TPS65224_MASK_BUCK_VMON_THR GENMASK(1, 0)
271 #define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
274 #define TPS65224_MASK_BUCK1_VSET GENMASK(7, 0)
275 #define TPS65224_MASK_BUCKS_VSET GENMASK(6, 0)
278 #define TPS6594_BIT_LDO_EN BIT(0)
286 #define TPS6594_BIT_LDORTC_DIS BIT(0)
290 #define TPS6594_MASK_LDO4_VSET GENMASK(6, 0)
294 #define TPS6594_MASK_LDO_OV_THR GENMASK(2, 0)
298 #define TPS65224_MASK_LDO_VMON_THR GENMASK(1, 0)
301 #define TPS6594_BIT_VMON_EN BIT(0)
310 #define TPS6594_MASK_VCCA_OV_THR GENMASK(2, 0)
312 #define TPS65224_MASK_VCCA_VMON_THR GENMASK(1, 0)
316 #define TPS6594_MASK_VMONX_OV_THR GENMASK(2, 0)
321 #define TPS65224_MASK_VMONX_THR GENMASK(1, 0)
324 #define TPS6594_BIT_GPIO_DIR BIT(0)
334 #define TPS6594_BIT_NRSTOUT_OD BIT(0)
342 #define TPS65224_BIT_NINT_ENDRV_PU_SEL BIT(0)
361 #define TPS6594_MASK_BUCK1_GRP_SEL GENMASK(1, 0)
367 #define TPS6594_MASK_BUCK5_GRP_SEL GENMASK(1, 0)
373 #define TPS6594_MASK_LDO4_GRP_SEL GENMASK(1, 0)
379 #define TPS6594_MASK_MCU_RAIL_TRIG GENMASK(1, 0)
385 #define TPS6594_MASK_MODERATE_ERR_TRIG GENMASK(1, 0)
405 #define TPS6594_BIT_VCCA_OV_MASK BIT(0)
413 #define TPS65224_BIT_BUCK1_UVOV_MASK BIT(0)
419 #define TPS65224_BIT_LDO1_UVOV_MASK BIT(0)
436 #define TPS6594_BIT_NPWRON_START_MASK BIT(0)
440 #define TPS65224_BIT_VSENSE_MASK BIT(0)
444 #define TPS6594_BIT_BIST_PASS_MASK BIT(0)
462 #define TPS6594_BIT_IMM_SHUTDOWN_MASK BIT(0)
470 #define TPS6594_BIT_COMM_FRM_ERR_MASK BIT(0)
477 #define TPS6594_BIT_EN_DRV_READBACK_MASK BIT(0)
481 #define TPS6594_BIT_ESM_SOC_PIN_MASK BIT(0)
489 #define TPS6594_BIT_BUCK_INT BIT(0)
499 #define TPS6594_BIT_BUCK1_2_INT BIT(0)
504 #define TPS65224_BIT_BUCK1_UVOV_INT BIT(0)
516 #define TPS6594_BIT_LDO1_2_INT BIT(0)
521 #define TPS65224_BIT_LDO1_UVOV_INT BIT(0)
535 #define TPS6594_BIT_VCCA_OV_INT BIT(0)
545 #define TPS6594_BIT_GPIO9_INT BIT(0)
554 #define TPS65224_BIT_GPIO1_INT BIT(0)
562 #define TPS6594_BIT_NPWRON_START_INT BIT(0)
563 #define TPS65224_BIT_VSENSE_INT BIT(0)
571 #define TPS6594_BIT_BIST_PASS_INT BIT(0)
581 #define TPS6594_BIT_TSD_ORD_INT BIT(0)
591 #define TPS6594_BIT_TSD_IMM_INT BIT(0)
597 #define TPS6594_BIT_IMM_SHUTDOWN_INT BIT(0)
608 #define TPS6594_BIT_COMM_FRM_ERR_INT BIT(0)
615 #define TPS6594_BIT_EN_DRV_READBACK_INT BIT(0)
619 #define TPS6594_BIT_ESM_SOC_PIN_INT BIT(0)
637 #define TPS6594_BIT_VCCA_OV_STAT BIT(0)
645 #define TPS65224_BIT_LDO1_UVOV_STAT BIT(0)
653 #define TPS65224_BIT_VSENSE_STAT BIT(0)
662 #define TPS6594_BIT_TSD_ORD_STAT BIT(0)
665 #define TPS6594_BIT_TSD_IMM_STAT BIT(0)
670 #define TPS6594_BIT_EN_DRV_READBACK_STAT BIT(0)
676 #define TPS6594_MASK_PGOOD_SEL_BUCK1 GENMASK(1, 0)
682 #define TPS6594_MASK_PGOOD_SEL_BUCK5 GENMASK(1, 0)
685 #define TPS6594_MASK_PGOOD_SEL_LDO1 GENMASK(1, 0)
691 #define TPS6594_BIT_PGOOD_SEL_VCCA BIT(0)
701 #define TPS6594_MASK_EXT_CLK_FREQ GENMASK(1, 0)
704 #define TPS6594_BIT_TWARN_LEVEL BIT(0)
713 #define TPS6594_BIT_BB_CHARGER_EN BIT(0)
721 #define TPS6594_BIT_ENABLE_DRV BIT(0)
724 #define TPS6594_BIT_NRSTOUT BIT(0)
733 #define TPS6594_BIT_EN_DRV_IN BIT(0)
741 #define TPS6594_MASK_RECOV_CNT GENMASK(3, 0)
744 #define TPS6594_MASK_RECOV_CNT_THR GENMASK(3, 0)
751 #define TPS6594_BIT_NSLEEP1B BIT(0)
758 #define TPS6594_MASK_SS_DEPTH GENMASK(1, 0)
765 #define TPS6594_MASK_PFSM_DELAY_STEP GENMASK(4, 0)
768 #define TPS6594_MASK_LDO1_RV_TIMEOUT GENMASK(3, 0)
772 #define TPS6594_MASK_LDO3_RV_TIMEOUT GENMASK(3, 0)
779 #define TPS6594_BIT_ESM_MCU_START BIT(0)
782 #define TPS6594_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)
788 #define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)
791 #define TPS6594_BIT_ESM_SOC_START BIT(0)
794 #define TPS65224_BIT_ESM_MCU_START BIT(0)
797 #define TPS6594_MASK_ESM_SOC_ERR_CNT_TH GENMASK(3, 0)
803 #define TPS65224_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)
809 #define TPS6594_MASK_ESM_SOC_ERR_CNT GENMASK(4, 0)
812 #define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)
815 #define TPS6594_BIT_REGISTER_LOCK_STATUS BIT(0)
818 #define TPS6594_MASK_VMON1_SLEW_RATE GENMASK(2, 0)
822 #define TPS65224_MASk_SRAM_UNLOCK_SEQ GENMASK(7, 0)
825 #define TPS65224_BIT_SRAM_WRITE_MODE BIT(0)
833 #define TPS65224_MASk_SRAM_SEL GENMASK(1, 0)
836 #define TPS65224_BIT_INCREMENT_RECOV_CNT BIT(0)
839 #define TPS65224_MASK_SILICON_REV GENMASK(7, 0)
842 #define TPS65224_MASK_CUSTOMER_NVM_ID GENMASK(7, 0)
845 #define TPS6594_BIT_SOFT_REBOOT BIT(0)
848 #define TPS6594_MASK_SECOND_0 GENMASK(3, 0)
852 #define TPS6594_MASK_MINUTE_0 GENMASK(3, 0)
856 #define TPS6594_MASK_HOUR_0 GENMASK(3, 0)
861 #define TPS6594_MASK_DAY_0 GENMASK(3, 0)
865 #define TPS6594_MASK_MONTH_0 GENMASK(3, 0)
869 #define TPS6594_MASK_YEAR_0 GENMASK(3, 0)
873 #define TPS6594_MASK_WEEK GENMASK(2, 0)
876 #define TPS6594_BIT_STOP_RTC BIT(0)
885 #define TPS6594_BIT_XTAL_EN BIT(0)
899 #define TPS6594_MASK_EVERY GENMASK(1, 0)
904 #define TPS6594_BIT_RESET_STATUS_RTC BIT(0)
907 #define TPS6594_BIT_I2C_SPI_SEL BIT(0)
913 #define TPS65224_BIT_ADC_START BIT(0)
920 #define TPS65224_MASK_ADC_RESULT_11_4 GENMASK(7, 0)
930 #define TPS6594_MASK_SCRATCH_PAD_1 GENMASK(7, 0)
933 #define TPS6594_MASK_SCRATCH_PAD_2 GENMASK(7, 0)
936 #define TPS6594_MASK_SCRATCH_PAD_3 GENMASK(7, 0)
939 #define TPS6594_MASK_SCRATCH_PAD_4 GENMASK(7, 0)
942 #define TPS6594_MASK_PFSM_DELAY1 GENMASK(7, 0)
945 #define TPS6594_MASK_PFSM_DELAY2 GENMASK(7, 0)
948 #define TPS6594_MASK_PFSM_DELAY3 GENMASK(7, 0)
951 #define TPS6594_MASK_PFSM_DELAY4 GENMASK(7, 0)
954 #define TPS65224_BIT_RUN_CRC_BIST BIT(0)
958 #define TPS65224_MASK_ADC_GAIN_COMP GENMASK(7, 0)
961 #define TPS65224_MASK_REGMAP_USER_CRC16_LOW GENMASK(7, 0)
964 #define TPS65224_MASK_REGMAP_USER_CRC16_HIGH GENMASK(7, 0)
967 #define TPS6594_MASK_WD_ANSWER GENMASK(7, 0)
970 #define TPS6594_MASK_WD_QUESTION GENMASK(3, 0)
975 #define TPS6594_MASK_WD_WIN1_CFG GENMASK(6, 0)
978 #define TPS6594_MASK_WD_WIN2_CFG GENMASK(6, 0)
981 #define TPS6594_MASK_WD_LONGWIN_CFG GENMASK(7, 0)
984 #define TPS6594_BIT_WD_RETURN_LONGWIN BIT(0)
991 #define TPS6594_MASK_WD_QUESTION_SEED GENMASK(3, 0)
996 #define TPS6594_BIT_WD_LONGWIN_TIMEOUT_INT BIT(0)
1006 #define TPS6594_MASK_WD_RST_TH GENMASK(2, 0)
1012 #define TPS6594_MASK_WD_FAIL_CNT GENMASK(3, 0)
1017 #define TPS6594_CRC8_POLYNOMIAL 0x07