Lines Matching +full:0 +full:x36c
18 sta2x11_sctl = 0,
53 #define PINMUX_TYPE_NONE 0
62 #define STA2X11_GPIO0 0
202 #define APBREG_BSR 0x00 /* Bridge Status Reg */
203 #define APBREG_PAER 0x08 /* Peripherals Address Error Reg */
204 #define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
205 #define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
206 #define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
207 #define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
208 #define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
214 #define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */
215 #define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */
216 #define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
217 #define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
218 #define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
219 #define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
220 #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
234 #define SCTL_SCCTL 0x00 /* System controller control register */
235 #define SCTL_ARMCFG 0x04 /* ARM configuration register */
236 #define SCTL_SCPLLCTL 0x08 /* PLL control status register */
243 #define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
245 #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff
251 #define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03
255 #define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
257 #define SCTL_SCRESFRACT_MASK 0x0000ffff
260 #define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
261 #define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
262 #define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
263 #define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
264 #define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
265 #define SCTL_SCGRST 0x28 /* Peripheral global reset */
266 #define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */
267 #define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
268 #define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
269 #define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
270 #define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */
271 #define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */
272 #define SCTL_SCINTREN 0x44 /* Interrupt enable */
273 #define SCTL_SCRISR 0x48 /* RAW interrupt status */
274 #define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
275 #define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
276 #define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */
277 #define SCTL_SCRSTSTA 0x58 /* Reset status register */
279 #define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0)
312 #define SCTL_SCPEREN0_UART0 (1 << 0)
345 #define SCTL_SCPEREN1_UART0 (1 << 0)
373 #define PCIE_EP1_FUNC3_0_INTR_REG 0x000
374 #define PCIE_EP1_FUNC7_4_INTR_REG 0x004
375 #define PCIE_EP2_FUNC3_0_INTR_REG 0x008
376 #define PCIE_EP2_FUNC7_4_INTR_REG 0x00c
377 #define PCIE_EP3_FUNC3_0_INTR_REG 0x010
378 #define PCIE_EP3_FUNC7_4_INTR_REG 0x014
379 #define PCIE_EP4_FUNC3_0_INTR_REG 0x018
380 #define PCIE_EP4_FUNC7_4_INTR_REG 0x01c
381 #define PCIE_INTR_ENABLE0_REG 0x020
382 #define PCIE_INTR_ENABLE1_REG 0x024
383 #define PCIE_EP1_FUNC_TC_REG 0x028
384 #define PCIE_EP2_FUNC_TC_REG 0x02c
385 #define PCIE_EP3_FUNC_TC_REG 0x030
386 #define PCIE_EP4_FUNC_TC_REG 0x034
387 #define PCIE_EP1_FUNC_F_REG 0x038
388 #define PCIE_EP2_FUNC_F_REG 0x03c
389 #define PCIE_EP3_FUNC_F_REG 0x040
390 #define PCIE_EP4_FUNC_F_REG 0x044
391 #define PCIE_PAB_AMBA_SW_RST_REG 0x048
392 #define PCIE_PM_STATUS_0_PORT_0_4 0x04c
393 #define PCIE_PM_STATUS_7_0_EP1 0x050
394 #define PCIE_PM_STATUS_7_0_EP2 0x054
395 #define PCIE_PM_STATUS_7_0_EP3 0x058
396 #define PCIE_PM_STATUS_7_0_EP4 0x05c
397 #define PCIE_DEV_ID_0_EP1_REG 0x060
398 #define PCIE_CC_REV_ID_0_EP1_REG 0x064
399 #define PCIE_DEV_ID_1_EP1_REG 0x068
400 #define PCIE_CC_REV_ID_1_EP1_REG 0x06c
401 #define PCIE_DEV_ID_2_EP1_REG 0x070
402 #define PCIE_CC_REV_ID_2_EP1_REG 0x074
403 #define PCIE_DEV_ID_3_EP1_REG 0x078
404 #define PCIE_CC_REV_ID_3_EP1_REG 0x07c
405 #define PCIE_DEV_ID_4_EP1_REG 0x080
406 #define PCIE_CC_REV_ID_4_EP1_REG 0x084
407 #define PCIE_DEV_ID_5_EP1_REG 0x088
408 #define PCIE_CC_REV_ID_5_EP1_REG 0x08c
409 #define PCIE_DEV_ID_6_EP1_REG 0x090
410 #define PCIE_CC_REV_ID_6_EP1_REG 0x094
411 #define PCIE_DEV_ID_7_EP1_REG 0x098
412 #define PCIE_CC_REV_ID_7_EP1_REG 0x09c
413 #define PCIE_DEV_ID_0_EP2_REG 0x0a0
414 #define PCIE_CC_REV_ID_0_EP2_REG 0x0a4
415 #define PCIE_DEV_ID_1_EP2_REG 0x0a8
416 #define PCIE_CC_REV_ID_1_EP2_REG 0x0ac
417 #define PCIE_DEV_ID_2_EP2_REG 0x0b0
418 #define PCIE_CC_REV_ID_2_EP2_REG 0x0b4
419 #define PCIE_DEV_ID_3_EP2_REG 0x0b8
420 #define PCIE_CC_REV_ID_3_EP2_REG 0x0bc
421 #define PCIE_DEV_ID_4_EP2_REG 0x0c0
422 #define PCIE_CC_REV_ID_4_EP2_REG 0x0c4
423 #define PCIE_DEV_ID_5_EP2_REG 0x0c8
424 #define PCIE_CC_REV_ID_5_EP2_REG 0x0cc
425 #define PCIE_DEV_ID_6_EP2_REG 0x0d0
426 #define PCIE_CC_REV_ID_6_EP2_REG 0x0d4
427 #define PCIE_DEV_ID_7_EP2_REG 0x0d8
428 #define PCIE_CC_REV_ID_7_EP2_REG 0x0dC
429 #define PCIE_DEV_ID_0_EP3_REG 0x0e0
430 #define PCIE_CC_REV_ID_0_EP3_REG 0x0e4
431 #define PCIE_DEV_ID_1_EP3_REG 0x0e8
432 #define PCIE_CC_REV_ID_1_EP3_REG 0x0ec
433 #define PCIE_DEV_ID_2_EP3_REG 0x0f0
434 #define PCIE_CC_REV_ID_2_EP3_REG 0x0f4
435 #define PCIE_DEV_ID_3_EP3_REG 0x0f8
436 #define PCIE_CC_REV_ID_3_EP3_REG 0x0fc
437 #define PCIE_DEV_ID_4_EP3_REG 0x100
438 #define PCIE_CC_REV_ID_4_EP3_REG 0x104
439 #define PCIE_DEV_ID_5_EP3_REG 0x108
440 #define PCIE_CC_REV_ID_5_EP3_REG 0x10c
441 #define PCIE_DEV_ID_6_EP3_REG 0x110
442 #define PCIE_CC_REV_ID_6_EP3_REG 0x114
443 #define PCIE_DEV_ID_7_EP3_REG 0x118
444 #define PCIE_CC_REV_ID_7_EP3_REG 0x11c
445 #define PCIE_DEV_ID_0_EP4_REG 0x120
446 #define PCIE_CC_REV_ID_0_EP4_REG 0x124
447 #define PCIE_DEV_ID_1_EP4_REG 0x128
448 #define PCIE_CC_REV_ID_1_EP4_REG 0x12c
449 #define PCIE_DEV_ID_2_EP4_REG 0x130
450 #define PCIE_CC_REV_ID_2_EP4_REG 0x134
451 #define PCIE_DEV_ID_3_EP4_REG 0x138
452 #define PCIE_CC_REV_ID_3_EP4_REG 0x13c
453 #define PCIE_DEV_ID_4_EP4_REG 0x140
454 #define PCIE_CC_REV_ID_4_EP4_REG 0x144
455 #define PCIE_DEV_ID_5_EP4_REG 0x148
456 #define PCIE_CC_REV_ID_5_EP4_REG 0x14c
457 #define PCIE_DEV_ID_6_EP4_REG 0x150
458 #define PCIE_CC_REV_ID_6_EP4_REG 0x154
459 #define PCIE_DEV_ID_7_EP4_REG 0x158
460 #define PCIE_CC_REV_ID_7_EP4_REG 0x15c
461 #define PCIE_SUBSYS_VEN_ID_REG 0x160
462 #define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164
463 #define PCIE_MIPHYP_SSC_EN_REG 0x168
464 #define PCIE_MIPHYP_ADDR_REG 0x16c
465 #define PCIE_L1_ASPM_READY_REG 0x170
466 #define PCIE_EXT_CFG_RDY_REG 0x174
467 #define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
468 #define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
469 #define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
470 #define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
471 #define DMA_IP_CTRL_REG 0x324
472 #define DISP_BRIDGE_PU_PD_CTRL_REG 0x328
473 #define VIP_PU_PD_CTRL_REG 0x32c
474 #define USB_MLB_PU_PD_CTRL_REG 0x330
475 #define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334
476 #define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338
477 #define UART_PU_PD_CTRL_REG 0x33c
478 #define ARM_Lock 0x340
479 #define SYS_IO_CHAR_REG1 0x344
480 #define SYS_IO_CHAR_REG2 0x348
481 #define SATA_CORE_ID_REG 0x34c
482 #define SATA_CTRL_REG 0x350
483 #define I2C_HSFIX_MISC_REG 0x354
484 #define SPARE2_RESERVED 0x358
485 #define SPARE3_RESERVED 0x35c
486 #define MASTER_LOCK_REG 0x368
487 #define SYSTEM_CONFIG_STATUS_REG 0x36c
488 #define MSP_CLK_CTRL_REG 0x39c
489 #define COMPENSATION_REG1 0x3c4
490 #define COMPENSATION_REG2 0x3c8
491 #define COMPENSATION_REG3 0x3cc
492 #define TEST_CTL_REG 0x3d0
497 #define STA2X11_SECR_CR 0x00
498 #define STA2X11_SECR_FVR0 0x10
499 #define STA2X11_SECR_FVR1 0x14