Lines Matching full:mtu5

27  * MTU5 contains 3 timer counter registers and is totaly different
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
50 /* 8-bit MTU5 register offset macros */
51 #define RZ_MTU3_TSTR		2 /* MTU5 Timer start register */
52 #define RZ_MTU3_TCNTCMPCLR	3 /* MTU5 Timer compare match clear register */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
78 /* 16-bit MTU5 register offset macros */
79 #define RZ_MTU3_TCNTU		0 /* MTU5 Timer counter U */
80 #define RZ_MTU3_TGRU		1 /* MTU5 Timer general register U */
81 #define RZ_MTU3_TCNTV		2 /* MTU5 Timer counter V */
82 #define RZ_MTU3_TGRV		3 /* MTU5 Timer general register V */
83 #define RZ_MTU3_TCNTW		4 /* MTU5 Timer counter W */
84 #define RZ_MTU3_TGRW		5 /* MTU5 Timer general register W */