Lines Matching +full:0 +full:x880

13 #define RZ_MTU3_TSTRA	0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB	0x880 /* Timer start register B */
17 #define RZ_MTU3_TDDRA	0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB	0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA	0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB	0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA	0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB	0x822 /* Timer cycle buffer register B */
23 #define RZ_MTU3_TCNTSA	0x020 /* Timer subcounter A */
24 #define RZ_MTU3_TCNTSB	0x820 /* Timer subcounter B */
32 #define RZ_MTU3_TIER	0 /* Timer interrupt register */
40 #define RZ_MTU3_TMDR1_MD		GENMASK(3, 0)
41 #define RZ_MTU3_TMDR1_MD_NORMAL		FIELD_PREP(RZ_MTU3_TMDR1_MD, 0)
64 #define RZ_MTU3_TCNT		0 /* Timer counter */
79 #define RZ_MTU3_TCNTU		0 /* MTU5 Timer counter U */
87 #define RZ_MTU3_TCNTLW		0 /* Timer longword counter */
91 #define RZ_MTU3_TMDR3		0x191 /* MTU1 Timer Mode Register 3 */
96 #define RZ_MTU3_TCR_TPCS	GENMASK(2, 0)
99 #define RZ_MTU3_TCR_CKEG_RISING	FIELD_PREP(RZ_MTU3_TCR_CKEG, 0)
102 #define RZ_MTU3_TIOR_IOA			GENMASK(3, 0)
103 #define RZ_MTU3_TIOR_OC_RETAIN			0