Lines Matching +full:0 +full:xf20

10 #define GIC_CPU_CTRL			0x00
11 #define GIC_CPU_PRIMASK 0x04
12 #define GIC_CPU_BINPOINT 0x08
13 #define GIC_CPU_INTACK 0x0c
14 #define GIC_CPU_EOI 0x10
15 #define GIC_CPU_RUNNINGPRI 0x14
16 #define GIC_CPU_HIGHPRI 0x18
17 #define GIC_CPU_ALIAS_BINPOINT 0x1c
18 #define GIC_CPU_ACTIVEPRIO 0xd0
19 #define GIC_CPU_IDENT 0xfc
20 #define GIC_CPU_DEACTIVATE 0x1000
22 #define GICC_ENABLE 0x1
23 #define GICC_INT_PRI_THRESHOLD 0xf0
25 #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0
38 #define GICC_IAR_INT_ID_MASK 0x3ff
40 #define GICC_DIS_BYPASS_MASK 0x1e0
42 #define GIC_DIST_CTRL 0x000
43 #define GIC_DIST_CTR 0x004
44 #define GIC_DIST_IIDR 0x008
45 #define GIC_DIST_IGROUP 0x080
46 #define GIC_DIST_ENABLE_SET 0x100
47 #define GIC_DIST_ENABLE_CLEAR 0x180
48 #define GIC_DIST_PENDING_SET 0x200
49 #define GIC_DIST_PENDING_CLEAR 0x280
50 #define GIC_DIST_ACTIVE_SET 0x300
51 #define GIC_DIST_ACTIVE_CLEAR 0x380
52 #define GIC_DIST_PRI 0x400
53 #define GIC_DIST_TARGET 0x800
54 #define GIC_DIST_CONFIG 0xc00
55 #define GIC_DIST_SOFTINT 0xf00
56 #define GIC_DIST_SGI_PENDING_CLEAR 0xf10
57 #define GIC_DIST_SGI_PENDING_SET 0xf20
59 #define GICD_ENABLE 0x1
60 #define GICD_DISABLE 0x0
61 #define GICD_INT_ACTLOW_LVLTRIG 0x0
62 #define GICD_INT_EN_CLR_X32 0xffffffff
63 #define GICD_INT_EN_SET_SGI 0x0000ffff
64 #define GICD_INT_EN_CLR_PPI 0xffff0000
66 #define GICD_IIDR_IMPLEMENTER_SHIFT 0
67 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
69 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
71 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
73 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
76 #define GICH_HCR 0x0
77 #define GICH_VTR 0x4
78 #define GICH_VMCR 0x8
79 #define GICH_MISR 0x10
80 #define GICH_EISR0 0x20
81 #define GICH_EISR1 0x24
82 #define GICH_ELRSR0 0x30
83 #define GICH_ELRSR1 0x34
84 #define GICH_APR 0xf0
85 #define GICH_LR0 0x100
87 #define GICH_HCR_EN (1 << 0)
91 #define GICH_LR_VIRTUALID (0x3ff << 0)
93 #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
102 #define GICH_VMCR_ENABLE_GRP0_SHIFT 0
116 #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
118 #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT)
120 #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
122 #define GICH_MISR_EOI (1 << 0)
126 #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT)