Lines Matching +full:reference +full:- +full:doubler +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0-only */
38  * struct ad9523_channel_spec - Output channel configuration
42  * @sync_ignore_en: Ignore chip-level SYNC signal.
49  * @channel_divider: 10-bit channel divider.
106  * struct ad9523_platform_data - platform specific information
109  * @refa_diff_rcv_en: REFA differential/single-ended input selection.
110  * @refb_diff_rcv_en: REFB differential/single-ended input selection.
111  * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
112  * @osc_in_diff_en: OSC differential/ single-ended input selection.
113  * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
114  * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
115  * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
116  * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
117  * @refa_r_div: PLL1 10-bit REFA R divider.
118  * @refb_r_div: PLL1 10-bit REFB R divider.
119  * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
125  * @ref_mode: Reference selection mode.
127  * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128  * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129  * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
136  * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
145 	/* Differential/ Single-Ended Input Configuration */
169 	/* Reference */