Lines Matching +full:0 +full:xc2000000
21 #define ZYNQMP_PM_VERSION_MINOR 0
27 #define ZYNQMP_TZ_VERSION_MINOR 0
33 #define PM_SIP_SVC 0xC2000000
36 #define GET_SIP_SVC_VERSION (0x8200ff03U)
39 #define SIP_SVC_VERSION_MAJOR (0U)
46 #define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0)
54 #define ZYNQMP_FAMILY_CODE 0x23
55 #define VERSAL_FAMILY_CODE 0x26
58 #define ALL_SUB_FAMILY_CODE 0x00
59 #define VERSAL_SUB_FAMILY_CODE 0x01
60 #define VERSALNET_SUB_FAMILY_CODE 0x03
65 #define API_ID_MASK GENMASK(7, 0)
70 #define FIRMWARE_VERSION_MASK 0xFFFFU
73 #define TF_A_PM_REGISTER_SGI 0xa04
74 #define PM_GET_TRUSTZONE_VERSION 0xa03
75 #define PM_SET_SUSPEND_MODE 0xa02
76 #define GET_CALLBACK_DATA 0xa01
98 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
99 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
100 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
101 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
104 #define PM_LOAD_PDI 0x701
105 #define PDI_SRC_DDR 0xF
112 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
113 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
117 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
122 #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U)
123 #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U)
124 #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U)
125 #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U)
127 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U)
128 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U)
129 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U)
130 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U)
131 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U)
132 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U)
133 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U)
136 #define SD_ITAPDLY 0xFF180314
137 #define SD_OTAPDLYSEL 0xFF180318
152 PM_MODULE_ID = 0x0,
153 XPM_MODULE_ID = 0x2,
154 XSEM_MODULE_ID = 0x3,
155 TF_A_MODULE_ID = 0xa,
165 PM_API_FEATURES = 0,
205 XST_PM_SUCCESS = 0,
219 IOCTL_GET_RPU_OPER_MODE = 0,
252 PM_QID_INVALID = 0,
270 PM_RPU_MODE_LOCKSTEP = 0,
275 PM_RPU_BOOTMEM_LOVEC = 0,
280 PM_RPU_TCM_SPLIT = 0,
285 PM_RESET_ACTION_RELEASE = 0,
433 PM_TAPDELAY_INPUT = 0,
438 PM_DLL_RESET_ASSERT = 0,
444 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
455 PM_PINCTRL_SLEW_RATE_FAST = 0,
460 PM_PINCTRL_BIAS_DISABLE = 0,
465 PM_PINCTRL_BIAS_PULL_DOWN = 0,
470 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
475 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
482 PM_PINCTRL_TRI_STATE_DISABLE = 0,
487 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
493 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
499 PM_TAPDELAY_NAND_DQS_IN = 0,
506 PM_TAPDELAY_BYPASS_DISABLE = 0,
511 PM_OSPI_MUX_SEL_DMA = 0,
516 PM_FEATURE_INVALID = 0,