Lines Matching +full:memory +full:- +full:controller
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
99 * fatal (maybe it is on an unused memory area,
100 * or the memory controller could recover from
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
139 * enum mem_type - memory types. For a more detailed reference, please see
145 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
146 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
147 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
148 * @MEM_SDR: SDR - Single data rate SDRAM
149 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
151 * for rank 0; pins 1 and 3 are for rank 1, if the memory
152 * is dual-rank.
158 * A registered memory has a buffer inside it, hiding
159 * part of the memory details to the memory controller.
161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
162 * Those memories are labeled as "PC2-" instead of "PC" to
164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
173 * x86 arch, but cell_edac PPC memory controller uses it.
177 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
178 * @MEM_LPDDR3: Low-Power DDR3 memory.
182 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
183 * @MEM_LPDDR4: Low-Power DDR4 memory.
186 * @MEM_LRDDR5: Load-Reduced DDR5 memory.
187 * @MEM_NVDIMM: Non-volatile RAM
189 * @MEM_HBM2: High bandwidth Memory Gen 2.
190 * @MEM_HBM3: High bandwidth Memory Gen 3.
256 * enum edac_type - Error Detection and Correction capabilities and mode
261 * @EDAC_EC: Error Checking - no correction
263 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
292 * enum scrub_type - scrubbing capabilities
326 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
336 * enum edac_mc_layer_type - memory controller hierarchy layer
338 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
339 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
340 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
341 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
342 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
343 * as a single memory area. This is used when
347 * be used when describing a memory stick location.
358 * struct edac_mc_layer - describes the memory controller hierarchy
373 * Maximum number of layers used by the memory controller to uniquely
374 * identify a single memory stick.
386 /* Memory location data */
393 enum dev_type dtype; /* memory device type */
394 enum mem_type mtype; /* memory dimm type */
408 * struct rank_info - contains the information for one DIMM rank
414 * the (csrow->csrow_idx, chan_idx) vector.
436 unsigned long page_mask; /* used for interleaving -
439 int csrow_idx; /* the chip-select row */
452 * struct errcount_attribute - used to store the several error counts
461 * struct edac_raw_error_desc - Raw error report structure
475 * @other_detail: other driver-specific detail about the error
494 /* MEMORY controller information structure
504 unsigned long mtype_cap; /* memory types supported by mc */
505 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
506 unsigned long edac_cap; /* configuration capabilities - this is
508 * difference is that the controller may be
517 /* Translates sdram memory scrub rate given in bytes/sec to the
523 /* Get the current sdram memory scrub rate from the internal
534 * Remaps memory pages: controller pages to physical pages.
537 /* FIXME - why not send the phys page to begin with? */
545 * Memory Controller hierarchy
547 * There are basically two types of memory controller: the ones that
548 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
549 * All old memory controllers enumerate memories per rank, but most
551 * When the memory controller is per rank, csbased is true.
564 * FIXME - what about controllers on other busses? - IDs must be
584 /* Additional top controller level attributes, but specified
588 * controller level.
600 * Used to report an error - by being at the global struct
601 * makes the memory allocated by the EDAC core
605 /* the internal state of this controller instance */
615 for ((dimm) = (mci)->dimms[0]; \
617 (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \
618 ? (mci)->dimms[(dimm)->idx + 1] \
622 * edac_get_dimm - Get DIMM info from a memory controller given by
632 * For 2 layers, this function is similar to allocating a two-dimensional
635 * For 3 layers, this function is similar to allocating a tri-dimensional
644 || (mci->n_layers > 1 && layer1 < 0) in edac_get_dimm()
645 || (mci->n_layers > 2 && layer2 < 0)) in edac_get_dimm()
650 if (mci->n_layers > 1) in edac_get_dimm()
651 index = index * mci->layers[1].size + layer1; in edac_get_dimm()
653 if (mci->n_layers > 2) in edac_get_dimm()
654 index = index * mci->layers[2].size + layer2; in edac_get_dimm()
656 if (index < 0 || index >= mci->tot_dimms) in edac_get_dimm()
659 if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) in edac_get_dimm()
662 return mci->dimms[index]; in edac_get_dimm()