1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18  * typedef dma_cookie_t - an opaque DMA cookie
20  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
31  * enum dma_status - DMA transaction status
46  * enum dma_transaction_type - DMA transaction types/indexes
49  * automatically set as dma devices are registered.
73  * enum dma_transfer_direction - dma transfer mode and direction indicator
89  * ----------------------------
91  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96  *  it is to be repeated and other per-transfer attributes.
103  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
111  * struct data_chunk - Element of scatter-gather list that makes a frame.
133  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
164  * struct dma_vec - DMA vector
166  * @len: Length in bytes of the DMA vector
174  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
176  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
178  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
181  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
182  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
183  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
186  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
190  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
218  * enum sum_check_bits - bit position of pq_check_flags
226  * enum sum_check_flags - result of async_{xor,pq}_zero_sum operations
227  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
228  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
237  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
243  * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
244  * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
249  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
255  * - DMA_DEV_TO_MEM:
263  * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
274  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
279  *   4. use dmaengine_desc_set_metadata_len()  to tell the DMA engine the amount
282  * - DMA_DEV_TO_MEM:
299  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
310  * struct dma_router - DMA router structure
311  * @dev: pointer to the DMA router device
320  * struct dma_chan - devices supply DMA channels, clients use them
321  * @device: ptr to the dma device who supplies this channel, always !%NULL
331  * @local: per-cpu pointer to a struct dma_chan_percpu
333  * @table_count: number of appearances in the mem-to-mem allocation table
334  * @router: pointer to the DMA router structure
335  * @route_data: channel specific data for the router
336  * @private: private data for certain client-channel associations
357 	/* DMA router */
358 	struct dma_router *router;  member
365  * struct dma_chan_dev - relate sysfs device node to backing channel device
369  * @chan_dma_dev: The channel is using custom/different dma-mapping
380  * enum dma_slave_buswidth - defines bus width of the DMA slave
397  * struct dma_slave_config - dma slave channel runtime config
403  * @src_addr: this is the physical address where DMA slave data
406  * @dst_addr: this is the physical address where DMA slave data
410  * register where DMA data shall be read. If the source
424  * an area instead of a single register to receive the data. Typically the DMA
435  * This struct is passed in as configuration data to a DMA engine
436  * in order to set up a certain channel for DMA transport at runtime.
437  * The DMA device/engine has to provide support for an additional
442  * follows: if it is likely that more than one DMA slave controllers in
463  * enum dma_residue_granularity - Granularity of the reported transfer residue
465  *  DMA channel is only able to tell whether a descriptor has been completed or
473  *  the hardware supports scatter-gather and the segment descriptor has a field
489  * struct dma_slave_caps - expose capabilities of a slave channel only
496  *	each type, the dma controller should set BIT(<TYPE>) and same
498  * @min_burst: min burst capability per-transfer
499  * @max_burst: max burst capability per-transfer
501  *	DMA tansaction with no software intervention for reinitialization.
527 	return dev_name(&chan->dev->device);  in dma_chan_name()
531  * typedef dma_filter_fn - callback filter for dma_request_channel
537  * being returned.  Where 'suitable' indicates a non-busy channel that
547 	DMA_TRANS_READ_FAILED,		/* Source DMA read failed */
548 	DMA_TRANS_WRITE_FAILED,		/* Destination DMA write failed */
588  * struct dma_async_tx_descriptor - async transaction descriptor
589  * ---dma generic offload fields---
590  * @cookie: tracking cookie for this transaction, set to -EBUSY if
601  * @callback_result: error result from a DMA transaction
603  * @unmap: hook for generic DMA unmap data
607  * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
608  *	DMA driver if metadata mode is supported with the descriptor
609  * ---async_tx api specific fields---
638 	kref_get(&unmap->kref);  in dma_set_unmap()
639 	tx->unmap = unmap;  in dma_set_unmap()
662 	if (!tx->unmap)  in dma_descriptor_unmap()
665 	dmaengine_unmap_put(tx->unmap);  in dma_descriptor_unmap()
666 	tx->unmap = NULL;  in dma_descriptor_unmap()
698 	spin_lock_bh(&txd->lock);  in txd_lock()
702 	spin_unlock_bh(&txd->lock);  in txd_unlock()
706 	txd->next = next;  in txd_chain()
707 	next->parent = txd;  in txd_chain()
711 	txd->parent = NULL;  in txd_clear_parent()
715 	txd->next = NULL;  in txd_clear_next()
719 	return txd->parent;  in txd_parent()
723 	return txd->next;  in txd_next()
728  * struct dma_tx_state - filled in to report the status of
730  * @last: last completed DMA cookie
731  * @used: last issued DMA cookie (i.e. the one in progress)
735  * @in_flight_bytes: amount of data in bytes cached by the DMA.
745  * enum dmaengine_alignment - defines alignment of the DMA async tx
761  * struct dma_slave_map - associates slave device and it's slave channel with
774  * struct dma_filter - information for slave device/channel to filter_fn/param
787  * struct dma_device - info on the entity supplying DMA services
789  * @chancnt: how many DMA channels are supported
790  * @privatecnt: how many DMA channels are requested by dma_request_channel
795  * @desc_metadata_modes: supported metadata modes by the DMA device
797  * @max_pq: maximum number of PQ sources and PQ-continue capability
803  * @dev: struct device reference for dma mapping api
812  *	each type, the dma controller should set BIT(<TYPE>) and same
814  * @min_burst: min burst capability per-transfer
815  * @max_burst: max burst capability per-transfer
817  *	DMA tansaction with no software intervention for reinitialization.
824  * @device_router_config: optional callback for DMA router configuration
825  * @device_free_chan_resources: release DMA channel's resources
834  * @device_prep_peripheral_dma_vec: prepares a scatter-gather DMA transfer,
837  * @device_prep_slave_sg: prepares a slave dma operation
838  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
842  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
843  * @device_caps: May be used to override the generic DMA slave capabilities
844  *	with per-channel specific ones
969 	if (chan->device->device_config)  in dmaengine_slave_config()
970 		return chan->device->device_config(chan, config);  in dmaengine_slave_config()
972 	return -ENOSYS;  in dmaengine_slave_config()
990 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_single()
993 	return chan->device->device_prep_slave_sg(chan, &sg, 1,  in dmaengine_prep_slave_single()
998  * dmaengine_prep_peripheral_dma_vec() - Prepare a DMA scatter-gather descriptor
1000  * @vecs: The array of DMA vectors that should be transferred
1001  * @nents: The number of DMA vectors in the array
1003  * @flags: DMA engine flags
1009 	if (!chan || !chan->device || !chan->device->device_prep_peripheral_dma_vec)  in dmaengine_prep_peripheral_dma_vec()
1012 	return chan->device->device_prep_peripheral_dma_vec(chan, vecs, nents,  in dmaengine_prep_peripheral_dma_vec()
1020 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_sg()
1023 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_slave_sg()
1034 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_rio_sg()
1037 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_rio_sg()
1047 	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)  in dmaengine_prep_dma_cyclic()
1050 	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,  in dmaengine_prep_dma_cyclic()
1058 	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)  in dmaengine_prep_interleaved_dma()
1061 	    !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))  in dmaengine_prep_interleaved_dma()
1064 	return chan->device->device_prep_interleaved_dma(chan, xt, flags);  in dmaengine_prep_interleaved_dma()
1068  * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1073  * @flags: DMA engine flags
1079 	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)  in dmaengine_prep_dma_memset()
1082 	return chan->device->device_prep_dma_memset(chan, dest, value,  in dmaengine_prep_dma_memset()
1090 	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)  in dmaengine_prep_dma_memcpy()
1093 	return chan->device->device_prep_dma_memcpy(chan, dest, src,  in dmaengine_prep_dma_memcpy()
1103 	return !!(chan->device->desc_metadata_modes & mode);  in dmaengine_is_metadata_mode_supported()
1117 	return -EINVAL;  in dmaengine_desc_attach_metadata()
1128 	return -EINVAL;  in dmaengine_desc_set_metadata_len()
1133  * dmaengine_terminate_all() - Terminate all active DMA transfers
1141 	if (chan->device->device_terminate_all)  in dmaengine_terminate_all()
1142 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_all()
1144 	return -ENOSYS;  in dmaengine_terminate_all()
1148  * dmaengine_terminate_async() - Terminate all active DMA transfers
1170 	if (chan->device->device_terminate_all)  in dmaengine_terminate_async()
1171 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_async()
1173 	return -EINVAL;  in dmaengine_terminate_async()
1177  * dmaengine_synchronize() - Synchronize DMA channel termination
1180  * Synchronizes to the DMA channel termination to the current context. When this
1190  * This function must only be called from non-atomic context and must not be
1198 	if (chan->device->device_synchronize)  in dmaengine_synchronize()
1199 		chan->device->device_synchronize(chan);  in dmaengine_synchronize()
1203  * dmaengine_terminate_sync() - Terminate all active DMA transfers
1208  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1212  * This function must only be called from non-atomic context and must not be
1231 	if (chan->device->device_pause)  in dmaengine_pause()
1232 		return chan->device->device_pause(chan);  in dmaengine_pause()
1234 	return -ENOSYS;  in dmaengine_pause()
1239 	if (chan->device->device_resume)  in dmaengine_resume()
1240 		return chan->device->device_resume(chan);  in dmaengine_resume()
1242 	return -ENOSYS;  in dmaengine_resume()
1248 	return chan->device->device_tx_status(chan, cookie, state);  in dmaengine_tx_status()
1253 	return desc->tx_submit(desc);  in dmaengine_submit()
1259 	return !(((1 << align) - 1) & (off1 | off2 | len));  in dmaengine_check_align()
1265 	return dmaengine_check_align(dev->copy_align, off1, off2, len);  in is_dma_copy_aligned()
1271 	return dmaengine_check_align(dev->xor_align, off1, off2, len);  in is_dma_xor_aligned()
1277 	return dmaengine_check_align(dev->pq_align, off1, off2, len);  in is_dma_pq_aligned()
1283 	return dmaengine_check_align(dev->fill_align, off1, off2, len);  in is_dma_fill_aligned()
1287 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)  in dma_set_maxpq()  argument
1289 	dma->max_pq = maxpq;  in dma_set_maxpq()
1291 		dma->max_pq |= DMA_HAS_PQ_CONTINUE;  in dma_set_maxpq()
1306 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)  in dma_dev_has_pq_continue()  argument
1308 	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;  in dma_dev_has_pq_continue()
1311 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)  in dma_dev_to_maxpq()  argument
1313 	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;  in dma_dev_to_maxpq()
1316 /* dma_maxpq - reduce maxpq in the face of continued operations
1317  * @dma - dma device with PQ capability
1318  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1329 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)  in dma_maxpq()  argument
1331 	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))  in dma_maxpq()
1332 		return dma_dev_to_maxpq(dma);  in dma_maxpq()
1334 		return dma_dev_to_maxpq(dma) - 1;  in dma_maxpq()
1336 		return dma_dev_to_maxpq(dma) - 3;  in dma_maxpq()
1356 	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,  in dmaengine_get_dst_icg()
1357 				 chunk->icg, chunk->dst_icg);  in dmaengine_get_dst_icg()
1363 	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,  in dmaengine_get_src_icg()
1364 				 chunk->icg, chunk->src_icg);  in dmaengine_get_src_icg()
1367 /* --- public DMA engine API --- */
1407 	tx->flags |= DMA_CTRL_ACK;  in async_tx_ack()
1412 	tx->flags &= ~DMA_CTRL_ACK;  in async_tx_clear_ack()
1417 	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;  in async_tx_test_ack()
1424 	set_bit(tx_type, dstp->bits);  in __dma_cap_set()
1431 	clear_bit(tx_type, dstp->bits);  in __dma_cap_clear()
1437 	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);  in __dma_cap_zero()
1444 	return test_bit(tx_type, srcp->bits);  in __dma_has_cap()
1451  * dma_async_issue_pending - flush pending transactions to HW
1452  * @chan: target DMA channel
1459 	chan->device->device_issue_pending(chan);  in dma_async_issue_pending()
1463  * dma_async_is_tx_complete - poll for transaction completion
1464  * @chan: DMA channel
1471  * the status of multiple cookies without re-checking hardware state.
1479 	status = chan->device->device_tx_status(chan, cookie, &state);  in dma_async_is_tx_complete()
1488  * dma_async_is_complete - test a cookie against chan state
1515 	st->last = last;  in dma_set_tx_state()
1516 	st->used = used;  in dma_set_tx_state()
1517 	st->residue = residue;  in dma_set_tx_state()
1560 	return ERR_PTR(-ENODEV);  in dma_request_chan()
1565 	return ERR_PTR(-ENODEV);  in dma_request_chan_by_mask()
1573 	return -ENXIO;  in dma_get_slave_caps()
1582 	ret = dma_get_slave_caps(tx->chan, &caps);  in dmaengine_desc_set_reuse()
1587 		return -EPERM;  in dmaengine_desc_set_reuse()
1589 	tx->flags |= DMA_CTRL_REUSE;  in dmaengine_desc_set_reuse()
1595 	tx->flags &= ~DMA_CTRL_REUSE;  in dmaengine_desc_clear_reuse()
1600 	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;  in dmaengine_desc_test_reuse()
1607 		return -EPERM;  in dmaengine_desc_free()
1609 	return desc->desc_free(desc);  in dmaengine_desc_free()
1612 /* --- DMA device --- */
1671 	if (chan->dev->chan_dma_dev)  in dmaengine_get_dma_device()
1672 		return &chan->dev->device;  in dmaengine_get_dma_device()
1674 	return chan->device->dev;  in dmaengine_get_dma_device()