Lines Matching +full:fixed +full:- +full:parent +full:- +full:rate
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
48 * @rate: Requested clock rate. This field will be adjusted by
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
60 unsigned long rate; member
69 unsigned long rate);
72 const struct clk_hw *parent,
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
133 * parent rate is an input parameter. It is up to the caller to
135 * driver cannot figure out a rate for this clock, it must return
136 * 0. Returns the calculated rate. Optional, but recommended - if
137 * this op is not set then clock rate will be initialized to 0.
139 * @round_rate: Given a target rate as input, returns the closest rate actually
140 * supported by the clock. The parent rate is an input/output
143 * @determine_rate: Given a target rate as input, returns the closest rate
144 * actually supported by the clock, and optionally the parent clock
145 * that should be used to provide the clock rate.
148 * possible parents specify a new parent by passing in the index
149 * as a u8 corresponding to the parent in either the .parent_names
152 * Returns 0 on success, -EERROR otherwise.
154 * @get_parent: Queries the hardware to determine the parent of a clock. The
156 * the parent clock. This index can be applied to either the
158 * translates the parent value read from hardware into an array
164 * @set_rate: Change the rate of this clock. The requested rate is specified
166 * of .round_rate call. The third argument gives the parent rate
168 * Returns 0 on success, -EERROR otherwise.
170 * @set_rate_and_parent: Change the rate and the parent of this clock. The
171 * requested rate is specified by the second argument, which
173 * third argument gives the parent rate which is likely helpful
175 * argument gives the parent index. This callback is optional (and
177 * for clocks that can tolerate switching the rate and the parent
179 * Returns 0 on success, -EERROR otherwise.
182 * is expressed in ppb (parts per billion). The parent accuracy is
184 * Returns the calculated accuracy. Optional - if this op is not
185 * set then clock accuracy will be initialized to parent accuracy
186 * or 0 (perfect clock) if clock has no parent.
189 * Returned values are 0-359 degrees on success, negative
194 * 0-359. Return 0 on success, otherwise -EERROR.
203 * and >= numerator) Return 0 on success, otherwise -EERROR.
205 * @init: Perform platform-specific initialization magic.
211 * such as rate or parents.
212 * Returns 0 on success, -EERROR otherwise.
216 * @debug_init: Set up type-specific debugfs entries for this clock. This
220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
247 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
253 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
256 unsigned long rate,
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
276 * @index: parent index local to provider registering clk (if @fw_name absent)
286 * struct clk_init_data - holds init data that's common to all clocks and is
292 * @parent_data: array of parent data for all possible parents (when some
297 * @flags: framework-level hints and quirks
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
319 * @clk: pointer to the per-user struct clk instance that can be used to call
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
389 * @parent_name: name of clock's parent
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
401 * @parent_data: parent clk data
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
415 * @parent_hw: pointer to parent clk
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
428 * @parent_data: parent clk data
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
442 * @parent_name: name of clock's parent
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
458 * @parent_hw: pointer to parent clk
459 * @flags: framework-specific flags
460 * @fixed_rate: non-adjustable clock rate
461 * @fixed_accuracy: non-adjustable clock accuracy
469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
473 * @parent_data: name of clock's parent
474 * @flags: framework-specific flags
475 * @fixed_rate: non-adjustable clock rate
476 * @fixed_accuracy: non-adjustable clock accuracy
484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
488 * @parent_data: name of clock's parent
489 * @flags: framework-specific flags
490 * @fixed_rate: non-adjustable clock rate
504 * struct clk_gate - gating clock
506 * @hw: handle between common and hardware-specific interfaces
509 * @flags: hardware-specific flags
515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519 * of this register, and mask of gate bits are in higher 16-bit of this
520 * register. While setting the gate bits, higher 16-bit should also be
522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
560 * clk_hw_register_gate - register a gate clock with the clock framework
563 * @parent_name: name of this clock's parent
564 * @flags: framework-specific flags for this clock
567 * @clk_gate_flags: gate-specific flags for this clock
576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
580 * @parent_hw: pointer to parent clk
581 * @flags: framework-specific flags for this clock
584 * @clk_gate_flags: gate-specific flags for this clock
593 * clk_hw_register_gate_parent_data - register a gate clock with the clock
597 * @parent_data: parent clk data
598 * @flags: framework-specific flags for this clock
601 * @clk_gate_flags: gate-specific flags for this clock
610 * devm_clk_hw_register_gate - register a gate clock with the clock framework
613 * @parent_name: name of this clock's parent
614 * @flags: framework-specific flags for this clock
617 * @clk_gate_flags: gate-specific flags for this clock
626 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
630 * @parent_hw: pointer to parent clk
631 * @flags: framework-specific flags for this clock
634 * @clk_gate_flags: gate-specific flags for this clock
644 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
648 * @parent_data: parent clk data
649 * @flags: framework-specific flags for this clock
652 * @clk_gate_flags: gate-specific flags for this clock
672 * struct clk_divider - adjustable divider clock
674 * @hw: handle between common and hardware-specific interfaces
685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
689 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
691 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
696 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
697 * of this register, and mask of divider bits are in higher 16-bit of this
698 * register. While setting the divider bits, higher 16-bit should also be
700 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
702 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
704 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
707 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
710 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
723 #define clk_div_mask(width) ((1 << (width)) - 1)
742 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
743 unsigned long rate, unsigned long *prate,
746 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
747 unsigned long rate, unsigned long *prate,
756 int divider_get_val(unsigned long rate, unsigned long parent_rate,
780 * clk_register_divider - register a divider clock with the clock framework
783 * @parent_name: name of clock's parent
784 * @flags: framework-specific flags
788 * @clk_divider_flags: divider-specific flags for this clock
797 * clk_hw_register_divider - register a divider clock with the clock framework
800 * @parent_name: name of clock's parent
801 * @flags: framework-specific flags
805 * @clk_divider_flags: divider-specific flags for this clock
814 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
818 * @parent_hw: pointer to parent clk
819 * @flags: framework-specific flags
823 * @clk_divider_flags: divider-specific flags for this clock
833 * clk_hw_register_divider_parent_data - register a divider clock with the clock
837 * @parent_data: parent clk data
838 * @flags: framework-specific flags
842 * @clk_divider_flags: divider-specific flags for this clock
852 * clk_hw_register_divider_table - register a table based divider clock with
856 * @parent_name: name of clock's parent
857 * @flags: framework-specific flags
861 * @clk_divider_flags: divider-specific flags for this clock
872 * clk_hw_register_divider_table_parent_hw - register a table based divider
876 * @parent_hw: pointer to parent clk
877 * @flags: framework-specific flags
881 * @clk_divider_flags: divider-specific flags for this clock
893 * clk_hw_register_divider_table_parent_data - register a table based divider
897 * @parent_data: parent clk data
898 * @flags: framework-specific flags
902 * @clk_divider_flags: divider-specific flags for this clock
915 * devm_clk_hw_register_divider - register a divider clock with the clock framework
918 * @parent_name: name of clock's parent
919 * @flags: framework-specific flags
923 * @clk_divider_flags: divider-specific flags for this clock
932 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
935 * @parent_hw: pointer to parent clk
936 * @flags: framework-specific flags
940 * @clk_divider_flags: divider-specific flags for this clock
951 * devm_clk_hw_register_divider_table - register a table based divider clock
955 * @parent_name: name of clock's parent
956 * @flags: framework-specific flags
960 * @clk_divider_flags: divider-specific flags for this clock
976 * struct clk_mux - multiplexer clock
978 * @hw: handle between common and hardware-specific interfaces
980 * @table: array of register values corresponding to the parent index
983 * @flags: hardware-specific flags
990 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
991 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
992 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
993 * register, and mask of mux bits are in higher 16-bit of this register.
994 * While setting the mux bits, higher 16-bit should also be updated to
996 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
998 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1000 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1048 (flags), (reg), (shift), BIT((width)) - 1, \
1068 (shift), BIT((width)) - 1, (clk_mux_flags), \
1074 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1080 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1087 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1092 (shift), BIT((width)) - 1, (clk_mux_flags), \
1099 (shift), BIT((width)) - 1, \
1107 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1119 * struct clk_fixed_factor - fixed multiplier and divider clock
1121 * @hw: handle between common and hardware-specific interfaces
1124 * @acc: fixed accuracy in ppb
1127 * Clock with a fixed multiplier and divider. The output frequency is the
1128 * parent clock rate divided by div and multiplied by mult.
1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1133 * parent clk accuracy.
1189 * struct clk_fractional_divider - adjustable fractional divider clock
1191 * @hw: handle between common and hardware-specific interfaces
1203 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1207 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1210 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1215 * caller's side the power-of-two capable prescaler exists.
1226 unsigned long rate, unsigned long *parent_rate,
1248 * struct clk_multiplier - adjustable multiplier clock
1250 * @hw: handle between common and hardware-specific interfaces
1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1262 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1264 * leaving the parent rate unmodified.
1265 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1267 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1289 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1291 * @hw: handle between common and hardware-specific interfaces
1292 * @mux_hw: handle between composite and hardware-specific mux clock
1293 * @rate_hw: handle between composite and hardware-specific rate clock
1294 * @gate_hw: handle between composite and hardware-specific gate clock
1296 * @rate_ops: clock ops for rate
1410 dst->clk = src->clk; in __clk_hw_set_clk()
1411 dst->core = src->core; in __clk_hw_set_clk()
1414 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, in divider_round_rate() argument
1420 rate, prate, table, width, flags); in divider_round_rate()
1423 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, in divider_ro_round_rate() argument
1430 rate, prate, table, width, flags, in divider_ro_round_rate()
1437 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1572 * fixed factor clk declarations.
1651 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1656 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1661 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1666 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()