1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
4  *  Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
77  * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88  * struct clk_ops -  Callback operations for hardware clocks; these are to
136  *		0. Returns the calculated rate. Optional, but recommended - if
152  *		Returns 0 on success, -EERROR otherwise.
168  *		Returns 0 on success, -EERROR otherwise.
179  *		Returns 0 on success, -EERROR otherwise.
184  *		Returns the calculated accuracy.  Optional - if	this op is not
189  *		Returned values are 0-359 degrees on success, negative
194  *		0-359. Return 0 on success, otherwise -EERROR.
203  *              and >= numerator) Return 0 on success, otherwise -EERROR.
205  * @init:	Perform platform-specific initialization magic.
212  *		Returns 0 on success, -EERROR otherwise.
216  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
220  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
230  * (eg. when a device is opened), and clk_enable when the clock is actually
272  * struct clk_parent_data - clk parent information
286  * struct clk_init_data - holds init data that's common to all clocks and is
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
374  * @dev: device that is registering this clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
385  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387  * @dev: device that is registering this clock
390  * @flags: framework-specific flags
391  * @fixed_rate: non-adjustable clock rate
397  * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
399  * @dev: device that is registering this clock
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
411  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
413  * @dev: device that is registering this clock
416  * @flags: framework-specific flags
417  * @fixed_rate: non-adjustable clock rate
424  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
426  * @dev: device that is registering this clock
429  * @flags: framework-specific flags
430  * @fixed_rate: non-adjustable clock rate
438  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
440  * @dev: device that is registering this clock
443  * @flags: framework-specific flags
444  * @fixed_rate: non-adjustable clock rate
445  * @fixed_accuracy: non-adjustable clock accuracy
454  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
456  * @dev: device that is registering this clock
459  * @flags: framework-specific flags
460  * @fixed_rate: non-adjustable clock rate
461  * @fixed_accuracy: non-adjustable clock accuracy
469  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
471  * @dev: device that is registering this clock
474  * @flags: framework-specific flags
475  * @fixed_rate: non-adjustable clock rate
476  * @fixed_accuracy: non-adjustable clock accuracy
484  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
486  * @dev: device that is registering this clock
489  * @flags: framework-specific flags
490  * @fixed_rate: non-adjustable clock rate
504  * struct clk_gate - gating clock
506  * @hw:		handle between common and hardware-specific interfaces
509  * @flags:	hardware-specific flags
515  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
518  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519  *	of this register, and mask of gate bits are in higher 16-bit of this
520  *	register.  While setting the gate bits, higher 16-bit should also be
522  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
541 struct clk_hw *__clk_hw_register_gate(struct device *dev,
548 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
555 struct clk *clk_register_gate(struct device *dev, const char *name,
560  * clk_hw_register_gate - register a gate clock with the clock framework
561  * @dev: device that is registering this clock
564  * @flags: framework-specific flags for this clock
567  * @clk_gate_flags: gate-specific flags for this clock
576  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
578  * @dev: device that is registering this clock
581  * @flags: framework-specific flags for this clock
584  * @clk_gate_flags: gate-specific flags for this clock
593  * clk_hw_register_gate_parent_data - register a gate clock with the clock
595  * @dev: device that is registering this clock
598  * @flags: framework-specific flags for this clock
601  * @clk_gate_flags: gate-specific flags for this clock
610  * devm_clk_hw_register_gate - register a gate clock with the clock framework
611  * @dev: device that is registering this clock
614  * @flags: framework-specific flags for this clock
617  * @clk_gate_flags: gate-specific flags for this clock
626  * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
628  * @dev: device that is registering this clock
631  * @flags: framework-specific flags for this clock
634  * @clk_gate_flags: gate-specific flags for this clock
644  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
646  * @dev: device that is registering this clock
649  * @flags: framework-specific flags for this clock
652  * @clk_gate_flags: gate-specific flags for this clock
672  * struct clk_divider - adjustable divider clock
674  * @hw:		handle between common and hardware-specific interfaces
677  * @width:	width of the divider bit field
685  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
689  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
691  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
696  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
697  *	of this register, and mask of divider bits are in higher 16-bit of this
698  *	register.  While setting the divider bits, higher 16-bit should also be
700  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
702  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
704  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
706  *	2^width of the field.
707  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
710  * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
717 	u8		width;  member
723 #define clk_div_mask(width)	((1 << (width)) - 1)  argument
741 		unsigned long flags, unsigned long width);
745 			       u8 width, unsigned long flags);
748 				  const struct clk_div_table *table, u8 width,
751 			   const struct clk_div_table *table, u8 width,
754 			      const struct clk_div_table *table, u8 width,
757 		const struct clk_div_table *table, u8 width,
760 struct clk_hw *__clk_hw_register_divider(struct device *dev,
764 		void __iomem *reg, u8 shift, u8 width,
767 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
771 		void __iomem *reg, u8 shift, u8 width,
774 struct clk *clk_register_divider_table(struct device *dev, const char *name,
776 		void __iomem *reg, u8 shift, u8 width,
780  * clk_register_divider - register a divider clock with the clock framework
781  * @dev: device registering this clock
784  * @flags: framework-specific flags
787  * @width: width of the bitfield
788  * @clk_divider_flags: divider-specific flags for this clock
791 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
794 				   (reg), (shift), (width),		       \
797  * clk_hw_register_divider - register a divider clock with the clock framework
798  * @dev: device registering this clock
801  * @flags: framework-specific flags
804  * @width: width of the bitfield
805  * @clk_divider_flags: divider-specific flags for this clock
809 				width, clk_divider_flags, lock)		      \  argument
811 				  NULL, (flags), (reg), (shift), (width),     \
814  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
816  * @dev: device registering this clock
819  * @flags: framework-specific flags
822  * @width: width of the bitfield
823  * @clk_divider_flags: divider-specific flags for this clock
827 					  shift, width, clk_divider_flags,    \  argument
830 				  NULL, (flags), (reg), (shift), (width),     \
833  * clk_hw_register_divider_parent_data - register a divider clock with the clock
835  * @dev: device registering this clock
838  * @flags: framework-specific flags
841  * @width: width of the bitfield
842  * @clk_divider_flags: divider-specific flags for this clock
846 					    reg, shift, width,		      \  argument
850 				  (width), (clk_divider_flags), NULL, (lock))
852  * clk_hw_register_divider_table - register a table based divider clock with
854  * @dev: device registering this clock
857  * @flags: framework-specific flags
860  * @width: width of the bitfield
861  * @clk_divider_flags: divider-specific flags for this clock
866 				      shift, width, clk_divider_flags, table, \  argument
869 				  NULL, (flags), (reg), (shift), (width),     \
872  * clk_hw_register_divider_table_parent_hw - register a table based divider
874  * @dev: device registering this clock
877  * @flags: framework-specific flags
880  * @width: width of the bitfield
881  * @clk_divider_flags: divider-specific flags for this clock
886 						reg, shift, width,	      \  argument
890 				  NULL, (flags), (reg), (shift), (width),     \
893  * clk_hw_register_divider_table_parent_data - register a table based divider
895  * @dev: device registering this clock
898  * @flags: framework-specific flags
901  * @width: width of the bitfield
902  * @clk_divider_flags: divider-specific flags for this clock
907 						  flags, reg, shift, width,   \  argument
912 				  (width), (clk_divider_flags), (table),      \
915  * devm_clk_hw_register_divider - register a divider clock with the clock framework
916  * @dev: device registering this clock
919  * @flags: framework-specific flags
922  * @width: width of the bitfield
923  * @clk_divider_flags: divider-specific flags for this clock
927 				width, clk_divider_flags, lock)		      \  argument
929 				  NULL, (flags), (reg), (shift), (width),     \
932  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
933  * @dev: device registering this clock
936  * @flags: framework-specific flags
939  * @width: width of the bitfield
940  * @clk_divider_flags: divider-specific flags for this clock
944 					       reg, shift, width,	      \  argument
948 				       (shift), (width), (clk_divider_flags), \
951  * devm_clk_hw_register_divider_table - register a table based divider clock
953  * @dev: device registering this clock
956  * @flags: framework-specific flags
959  * @width: width of the bitfield
960  * @clk_divider_flags: divider-specific flags for this clock
965 					   reg, shift, width,		      \  argument
969 				       (width), (clk_divider_flags), (table), \
976  * struct clk_mux - multiplexer clock
978  * @hw:		handle between common and hardware-specific interfaces
983  * @flags:	hardware-specific flags
990  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
991  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
992  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
993  *	register, and mask of mux bits are in higher 16-bit of this register.
994  *	While setting the mux bits, higher 16-bit should also be updated to
996  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
998  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1000  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1026 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
1033 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1040 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1046 			 shift, width, clk_mux_flags, lock)		      \  argument
1048 			       (flags), (reg), (shift), BIT((width)) - 1,     \
1065 			    shift, width, clk_mux_flags, lock)		      \  argument
1068 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1071 				reg, shift, width, clk_mux_flags, lock)	      \  argument
1074 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1076 					flags, reg, shift, width,	      \  argument
1080 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1083 					      width, clk_mux_flags, table,    \  argument
1087 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1089 			    shift, width, clk_mux_flags, lock)		      \  argument
1092 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1096 					    width, clk_mux_flags, lock)       \  argument
1099 				   (shift), BIT((width)) - 1,		      \
1103 					      width, clk_mux_flags, table,    \  argument
1107 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1119  * struct clk_fixed_factor - fixed multiplier and divider clock
1121  * @hw:		handle between common and hardware-specific interfaces
1132  * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1149 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1153 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1156 struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
1159 struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1163 struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
1167 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1170 struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
1173 struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1177 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1181 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1185 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1189  * struct clk_fractional_divider - adjustable fractional divider clock
1191  * @hw:		handle between common and hardware-specific interfaces
1194  * @mwidth:	width of the numerator bit field
1196  * @nwidth:	width of the denominator bit field
1203  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1207  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1210  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1215  *	caller's side the power-of-two capable prescaler exists.
1237 struct clk *clk_register_fractional_divider(struct device *dev,
1241 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1248  * struct clk_multiplier - adjustable multiplier clock
1250  * @hw:		handle between common and hardware-specific interfaces
1253  * @width:	width of the multiplier bit field
1260  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1265  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1267  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1275 	u8		width;  member
1289  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1291  * @hw:		handle between common and hardware-specific interfaces
1292  * @mux_hw:	handle between composite and hardware-specific mux clock
1293  * @rate_hw:	handle between composite and hardware-specific rate clock
1294  * @gate_hw:	handle between composite and hardware-specific gate clock
1314 struct clk *clk_register_composite(struct device *dev, const char *name,
1320 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1327 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1333 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1340 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1349 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1350 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1352 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1353 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1373 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1410 	dst->clk = src->clk;  in __clk_hw_set_clk()
1411 	dst->core = src->core;  in __clk_hw_set_clk()
1417 				      u8 width, unsigned long flags)  in divider_round_rate()  argument
1420 					 rate, prate, table, width, flags);  in divider_round_rate()
1426 					 u8 width, unsigned long flags,  in divider_ro_round_rate()  argument
1430 					    rate, prate, table, width, flags,  in divider_ro_round_rate()
1459  * routines, one at of_clk_init(), and one at platform device probe
1605 int devm_of_clk_add_hw_provider(struct device *dev,
1639 static inline int devm_of_clk_add_hw_provider(struct device *dev,  in devm_of_clk_add_hw_provider()
1651 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1656 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1661 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1666 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()