Lines Matching +full:clock +full:- +full:name

1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
89 * be provided by the clock implementation, and will be called by drivers
92 * @prepare: Prepare the clock for enabling. This must not return until
93 * the clock is fully prepared, and it's safe to call clk_enable.
94 * This callback is intended to allow clock implementations to
98 * @unprepare: Release the clock from its prepared state. This will typically
102 * @is_prepared: Queries the hardware to determine if the clock is prepared.
106 * @unprepare_unused: Unprepare the clock atomically. Only called from
110 * @enable: Enable the clock atomically. This must not return until the
111 * clock is generating a valid clock signal, usable by consumer
115 * @disable: Disable the clock atomically. Called with enable_lock held.
118 * @is_enabled: Queries the hardware to determine if the clock is enabled.
122 * @disable_unused: Disable the clock atomically. Only called from
127 * @save_context: Save the context of the clock in prepration for poweroff.
129 * @restore_context: Restore the context of the clock after a restoration
132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
135 * driver cannot figure out a rate for this clock, it must return
136 * 0. Returns the calculated rate. Optional, but recommended - if
137 * this op is not set then clock rate will be initialized to 0.
140 * supported by the clock. The parent rate is an input/output
144 * actually supported by the clock, and optionally the parent clock
145 * that should be used to provide the clock rate.
147 * @set_parent: Change the input source of this clock; for clocks with multiple
152 * Returns 0 on success, -EERROR otherwise.
154 * @get_parent: Queries the hardware to determine the parent of a clock. The
156 * the parent clock. This index can be applied to either the
159 * index. Currently only called when the clock is initialized by
164 * @set_rate: Change the rate of this clock. The requested rate is specified
168 * Returns 0 on success, -EERROR otherwise.
170 * @set_rate_and_parent: Change the rate and the parent of this clock. The
179 * Returns 0 on success, -EERROR otherwise.
181 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
184 * Returns the calculated accuracy. Optional - if this op is not
185 * set then clock accuracy will be initialized to parent accuracy
186 * or 0 (perfect clock) if clock has no parent.
188 * @get_phase: Queries the hardware to get the current phase of a clock.
189 * Returned values are 0-359 degrees on success, negative
192 * @set_phase: Shift the phase this clock signal in degrees specified
194 * 0-359. Return 0 on success, otherwise -EERROR.
197 * of a clock. Returned values denominator cannot be 0 and must be
200 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
203 * and >= numerator) Return 0 on success, otherwise -EERROR.
205 * @init: Perform platform-specific initialization magic.
206 * This is not used by any of the basic clock types.
209 * clock. It may also be used dynamic resource allocation is
210 * required. It shall not used to deal with clock parameters,
212 * Returns 0 on success, -EERROR otherwise.
216 * @debug_init: Set up type-specific debugfs entries for this clock. This
218 * clock has been created. The dentry pointer representing that
220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
225 * (prepare) contexts. If enabling a clock requires code that might sleep,
226 * this must be done in clk_prepare. Clock enable code that will never be
229 * Typically, drivers will call clk_prepare when a clock may be needed later
230 * (eg. when a device is opened), and clk_enable when the clock is actually
272 * struct clk_parent_data - clk parent information
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
281 const char *name; member
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
289 * @name: clock name
290 * @ops: operations this clock supports
297 * @flags: framework-level hints and quirks
300 const char *name; member
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
319 * @clk: pointer to the per-user struct clk instance that can be used to call
323 * with the common clock framework. This pointer will be set to NULL once
333 * DOC: Basic clock implementations common to many platforms
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
363 struct device_node *np, const char *name,
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ argument
381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387 * @dev: device that is registering this clock
388 * @name: name of this clock
389 * @parent_name: name of clock's parent
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
393 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ argument
394 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
405 #define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \ argument
407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
412 * the clock framework
413 * @dev: device that is registering this clock
414 * @name: name of this clock
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
419 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ argument
421 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
425 * the clock framework
426 * @dev: device that is registering this clock
427 * @name: name of this clock
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
432 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \ argument
434 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
439 * the clock framework
440 * @dev: device that is registering this clock
441 * @name: name of this clock
442 * @parent_name: name of clock's parent
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
447 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ argument
450 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
455 * clock with the clock framework
456 * @dev: device that is registering this clock
457 * @name: name of this clock
459 * @flags: framework-specific flags
460 * @fixed_rate: non-adjustable clock rate
461 * @fixed_accuracy: non-adjustable clock accuracy
463 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ argument
465 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
470 * clock with the clock framework
471 * @dev: device that is registering this clock
472 * @name: name of this clock
473 * @parent_data: name of clock's parent
474 * @flags: framework-specific flags
475 * @fixed_rate: non-adjustable clock rate
476 * @fixed_accuracy: non-adjustable clock accuracy
478 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ argument
480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
485 * the clock framework
486 * @dev: device that is registering this clock
487 * @name: name of this clock
488 * @parent_data: name of clock's parent
489 * @flags: framework-specific flags
490 * @fixed_rate: non-adjustable clock rate
492 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ argument
494 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
504 * struct clk_gate - gating clock
506 * @hw: handle between common and hardware-specific interfaces
509 * @flags: hardware-specific flags
512 * Clock which can gate its output. Implements .enable & .disable
515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
516 * enable the clock. Setting this flag does the opposite: setting the bit
517 * disable the clock and clearing it enables the clock
518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519 * of this register, and mask of gate bits are in higher 16-bit of this
520 * register. While setting the gate bits, higher 16-bit should also be
522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
542 struct device_node *np, const char *name,
549 struct device_node *np, const char *name,
555 struct clk *clk_register_gate(struct device *dev, const char *name,
560 * clk_hw_register_gate - register a gate clock with the clock framework
561 * @dev: device that is registering this clock
562 * @name: name of this clock
563 * @parent_name: name of this clock's parent
564 * @flags: framework-specific flags for this clock
565 * @reg: register address to control gating of this clock
566 * @bit_idx: which bit in the register controls gating of this clock
567 * @clk_gate_flags: gate-specific flags for this clock
568 * @lock: shared register lock for this clock
570 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ argument
572 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
578 * @dev: device that is registering this clock
579 * @name: name of this clock
581 * @flags: framework-specific flags for this clock
582 * @reg: register address to control gating of this clock
583 * @bit_idx: which bit in the register controls gating of this clock
584 * @clk_gate_flags: gate-specific flags for this clock
585 * @lock: shared register lock for this clock
587 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ argument
589 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
593 * clk_hw_register_gate_parent_data - register a gate clock with the clock
595 * @dev: device that is registering this clock
596 * @name: name of this clock
598 * @flags: framework-specific flags for this clock
599 * @reg: register address to control gating of this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
602 * @lock: shared register lock for this clock
604 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ argument
606 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
610 * devm_clk_hw_register_gate - register a gate clock with the clock framework
611 * @dev: device that is registering this clock
612 * @name: name of this clock
613 * @parent_name: name of this clock's parent
614 * @flags: framework-specific flags for this clock
615 * @reg: register address to control gating of this clock
616 * @bit_idx: which bit in the register controls gating of this clock
617 * @clk_gate_flags: gate-specific flags for this clock
618 * @lock: shared register lock for this clock
620 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ argument
622 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
626 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
628 * @dev: device that is registering this clock
629 * @name: name of this clock
631 * @flags: framework-specific flags for this clock
632 * @reg: register address to control gating of this clock
633 * @bit_idx: which bit in the register controls gating of this clock
634 * @clk_gate_flags: gate-specific flags for this clock
635 * @lock: shared register lock for this clock
637 #define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ argument
640 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
644 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
645 * clock framework
646 * @dev: device that is registering this clock
647 * @name: name of this clock
649 * @flags: framework-specific flags for this clock
650 * @reg: register address to control gating of this clock
651 * @bit_idx: which bit in the register controls gating of this clock
652 * @clk_gate_flags: gate-specific flags for this clock
653 * @lock: shared register lock for this clock
655 #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ argument
658 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
672 * struct clk_divider - adjustable divider clock
674 * @hw: handle between common and hardware-specific interfaces
681 * Clock with an adjustable divider affecting its output frequency. Implements
685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
689 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
691 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
694 * zero divisor by not modifying their input clock
696 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
697 * of this register, and mask of divider bits are in higher 16-bit of this
698 * register. While setting the divider bits, higher 16-bit should also be
700 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
702 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
703 * not be changed by the clock framework.
704 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
707 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
710 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
723 #define clk_div_mask(width) ((1 << (width)) - 1)
761 struct device_node *np, const char *name,
768 struct device_node *np, const char *name,
774 struct clk *clk_register_divider_table(struct device *dev, const char *name,
780 * clk_register_divider - register a divider clock with the clock framework
781 * @dev: device registering this clock
782 * @name: name of this clock
783 * @parent_name: name of clock's parent
784 * @flags: framework-specific flags
788 * @clk_divider_flags: divider-specific flags for this clock
789 * @lock: shared register lock for this clock
791 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ argument
793 clk_register_divider_table((dev), (name), (parent_name), (flags), \
797 * clk_hw_register_divider - register a divider clock with the clock framework
798 * @dev: device registering this clock
799 * @name: name of this clock
800 * @parent_name: name of clock's parent
801 * @flags: framework-specific flags
805 * @clk_divider_flags: divider-specific flags for this clock
806 * @lock: shared register lock for this clock
808 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ argument
810 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
814 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
816 * @dev: device registering this clock
817 * @name: name of this clock
819 * @flags: framework-specific flags
823 * @clk_divider_flags: divider-specific flags for this clock
824 * @lock: shared register lock for this clock
826 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ argument
829 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
833 * clk_hw_register_divider_parent_data - register a divider clock with the clock
835 * @dev: device registering this clock
836 * @name: name of this clock
838 * @flags: framework-specific flags
842 * @clk_divider_flags: divider-specific flags for this clock
843 * @lock: shared register lock for this clock
845 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ argument
848 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
852 * clk_hw_register_divider_table - register a table based divider clock with
853 * the clock framework
854 * @dev: device registering this clock
855 * @name: name of this clock
856 * @parent_name: name of clock's parent
857 * @flags: framework-specific flags
861 * @clk_divider_flags: divider-specific flags for this clock
863 * @lock: shared register lock for this clock
865 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ argument
868 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
872 * clk_hw_register_divider_table_parent_hw - register a table based divider
873 * clock with the clock framework
874 * @dev: device registering this clock
875 * @name: name of this clock
877 * @flags: framework-specific flags
881 * @clk_divider_flags: divider-specific flags for this clock
883 * @lock: shared register lock for this clock
885 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ argument
889 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
893 * clk_hw_register_divider_table_parent_data - register a table based divider
894 * clock with the clock framework
895 * @dev: device registering this clock
896 * @name: name of this clock
898 * @flags: framework-specific flags
902 * @clk_divider_flags: divider-specific flags for this clock
904 * @lock: shared register lock for this clock
906 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ argument
910 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
915 * devm_clk_hw_register_divider - register a divider clock with the clock framework
916 * @dev: device registering this clock
917 * @name: name of this clock
918 * @parent_name: name of clock's parent
919 * @flags: framework-specific flags
923 * @clk_divider_flags: divider-specific flags for this clock
924 * @lock: shared register lock for this clock
926 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ argument
928 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
932 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
933 * @dev: device registering this clock
934 * @name: name of this clock
936 * @flags: framework-specific flags
940 * @clk_divider_flags: divider-specific flags for this clock
941 * @lock: shared register lock for this clock
943 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ argument
946 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
951 * devm_clk_hw_register_divider_table - register a table based divider clock
952 * with the clock framework (devres variant)
953 * @dev: device registering this clock
954 * @name: name of this clock
955 * @parent_name: name of clock's parent
956 * @flags: framework-specific flags
960 * @clk_divider_flags: divider-specific flags for this clock
962 * @lock: shared register lock for this clock
964 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ argument
967 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
976 * struct clk_mux - multiplexer clock
978 * @hw: handle between common and hardware-specific interfaces
983 * @flags: hardware-specific flags
986 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
990 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
991 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
992 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
993 * register, and mask of mux bits are in higher 16-bit of this register.
994 * While setting the mux bits, higher 16-bit should also be updated to
996 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
998 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1000 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1027 const char *name, u8 num_parents,
1034 const char *name, u8 num_parents,
1040 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1045 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ argument
1047 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
1048 (flags), (reg), (shift), BIT((width)) - 1, \
1050 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ argument
1053 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1057 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ argument
1060 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1064 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ argument
1066 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1068 (shift), BIT((width)) - 1, (clk_mux_flags), \
1070 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ argument
1072 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1074 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1075 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ argument
1078 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1080 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1081 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ argument
1085 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1087 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1088 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ argument
1090 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1092 (shift), BIT((width)) - 1, (clk_mux_flags), \
1094 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ argument
1097 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1099 (shift), BIT((width)) - 1, \
1101 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ argument
1105 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1107 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1119 * struct clk_fixed_factor - fixed multiplier and divider clock
1121 * @hw: handle between common and hardware-specific interfaces
1127 * Clock with a fixed multiplier and divider. The output frequency is the
1128 * parent clock rate divided by div and multiplied by mult.
1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1149 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1154 const char *name, const char *parent_name, unsigned long flags,
1157 struct device_node *np, const char *name, const char *fw_name,
1160 struct device_node *np, const char *name, const char *fw_name,
1164 const char *name, unsigned int index, unsigned long flags,
1168 const char *name, const char *parent_name, unsigned long flags,
1171 struct device_node *np, const char *name, const char *fw_name,
1174 struct device_node *np, const char *name, const char *fw_name,
1178 const char *name, unsigned int index, unsigned long flags,
1182 const char *name, const struct clk_hw *parent_hw,
1186 const char *name, const struct clk_hw *parent_hw,
1189 * struct clk_fractional_divider - adjustable fractional divider clock
1191 * @hw: handle between common and hardware-specific interfaces
1197 * @approximation: clk driver's callback for calculating the divider clock
1200 * Clock with adjustable fractional divider affecting its output frequency.
1203 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1207 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1210 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1215 * caller's side the power-of-two capable prescaler exists.
1238 const char *name, const char *parent_name, unsigned long flags,
1242 const char *name, const char *parent_name, unsigned long flags,
1248 * struct clk_multiplier - adjustable multiplier clock
1250 * @hw: handle between common and hardware-specific interfaces
1256 * Clock with an adjustable multiplier affecting its output frequency.
1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1262 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1265 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1267 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1289 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1291 * @hw: handle between common and hardware-specific interfaces
1292 * @mux_hw: handle between composite and hardware-specific mux clock
1293 * @rate_hw: handle between composite and hardware-specific rate clock
1294 * @gate_hw: handle between composite and hardware-specific gate clock
1295 * @mux_ops: clock ops for mux
1296 * @rate_ops: clock ops for rate
1297 * @gate_ops: clock ops for gate
1314 struct clk *clk_register_composite(struct device *dev, const char *name,
1320 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1327 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1334 const char *name,
1341 const char *name, const struct clk_parent_data *parent_data,
1391 struct clk *__clk_lookup(const char *name);
1410 dst->clk = src->clk; in __clk_hw_set_clk()
1411 dst->core = src->core; in __clk_hw_set_clk()
1435 * FIXME clock api without lock protection
1449 #define CLK_OF_DECLARE(name, compat, fn) \ argument
1450 static void __init __##name##_of_clk_init_declare(struct device_node *np) \
1455 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
1461 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ argument
1462 static void __init name##_of_clk_init_driver(struct device_node *np) \
1467 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1472 .name = _name, \
1481 .name = _name, \
1495 .name = _name, \
1504 .name = _name, \
1515 .name = _name, \
1524 .name = _name, \
1533 .name = _name, \
1542 .name = _name, \
1651 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1656 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1661 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1666 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()