Lines Matching +full:12 +full:bit +full:- +full:clk +full:- +full:divider
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
36 struct clk;
42 * struct clk_rate_request - Structure encoding the clk constraints that
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
136 * 0. Returns the calculated rate. Optional, but recommended - if
152 * Returns 0 on success, -EERROR otherwise.
168 * Returns 0 on success, -EERROR otherwise.
179 * Returns 0 on success, -EERROR otherwise.
184 * Returns the calculated accuracy. Optional - if this op is not
189 * Returned values are 0-359 degrees on success, negative
194 * 0-359. Return 0 on success, otherwise -EERROR.
203 * and >= numerator) Return 0 on success, otherwise -EERROR.
205 * @init: Perform platform-specific initialization magic.
212 * Returns 0 on success, -EERROR otherwise.
216 * @debug_init: Set up type-specific debugfs entries for this clock. This
220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
276 * @index: parent index local to provider registering clk (if @fw_name absent)
286 * struct clk_init_data - holds init data that's common to all clocks and is
293 * parents are external to the clk controller)
295 * are internal to the clk controller)
297 * @flags: framework-level hints and quirks
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
313 * clk_foo and then referenced by the struct clk instance that uses struct
319 * @clk: pointer to the per-user struct clk instance that can be used to call
320 * into the clk API
328 struct clk *clk; member
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
359 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
401 * @parent_data: parent clk data
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
415 * @parent_hw: pointer to parent clk
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
428 * @parent_data: parent clk data
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
458 * @parent_hw: pointer to parent clk
459 * @flags: framework-specific flags
460 * @fixed_rate: non-adjustable clock rate
461 * @fixed_accuracy: non-adjustable clock accuracy
469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
474 * @flags: framework-specific flags
475 * @fixed_rate: non-adjustable clock rate
476 * @fixed_accuracy: non-adjustable clock accuracy
484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
489 * @flags: framework-specific flags
490 * @fixed_rate: non-adjustable clock rate
498 void clk_unregister_fixed_rate(struct clk *clk);
504 * struct clk_gate - gating clock
506 * @hw: handle between common and hardware-specific interfaces
508 * @bit_idx: single bit controlling gate
509 * @flags: hardware-specific flags
515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
516 * enable the clock. Setting this flag does the opposite: setting the bit
518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519 * of this register, and mask of gate bits are in higher 16-bit of this
520 * register. While setting the gate bits, higher 16-bit should also be
522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
536 #define CLK_GATE_SET_TO_DISABLE BIT(0)
537 #define CLK_GATE_HIWORD_MASK BIT(1)
538 #define CLK_GATE_BIG_ENDIAN BIT(2)
555 struct clk *clk_register_gate(struct device *dev, const char *name,
560 * clk_hw_register_gate - register a gate clock with the clock framework
564 * @flags: framework-specific flags for this clock
566 * @bit_idx: which bit in the register controls gating of this clock
567 * @clk_gate_flags: gate-specific flags for this clock
576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
580 * @parent_hw: pointer to parent clk
581 * @flags: framework-specific flags for this clock
583 * @bit_idx: which bit in the register controls gating of this clock
584 * @clk_gate_flags: gate-specific flags for this clock
593 * clk_hw_register_gate_parent_data - register a gate clock with the clock
597 * @parent_data: parent clk data
598 * @flags: framework-specific flags for this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
610 * devm_clk_hw_register_gate - register a gate clock with the clock framework
614 * @flags: framework-specific flags for this clock
616 * @bit_idx: which bit in the register controls gating of this clock
617 * @clk_gate_flags: gate-specific flags for this clock
626 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
630 * @parent_hw: pointer to parent clk
631 * @flags: framework-specific flags for this clock
633 * @bit_idx: which bit in the register controls gating of this clock
634 * @clk_gate_flags: gate-specific flags for this clock
644 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
648 * @parent_data: parent clk data
649 * @flags: framework-specific flags for this clock
651 * @bit_idx: which bit in the register controls gating of this clock
652 * @clk_gate_flags: gate-specific flags for this clock
662 void clk_unregister_gate(struct clk *clk);
672 * struct clk_divider - adjustable divider clock
674 * @hw: handle between common and hardware-specific interfaces
675 * @reg: register containing the divider
676 * @shift: shift to the divider bit field
677 * @width: width of the divider bit field
678 * @table: array of value/divider pairs, last entry should have div = 0
681 * Clock with an adjustable divider affecting its output frequency. Implements
685 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
686 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
689 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
691 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
696 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
697 * of this register, and mask of divider bits are in higher 16-bit of this
698 * register. While setting the divider bits, higher 16-bit should also be
699 * updated to indicate changing divider bits.
700 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
702 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
704 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
707 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
708 * for the divider register. Setting this flag makes the register accesses
710 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
723 #define clk_div_mask(width) ((1 << (width)) - 1)
726 #define CLK_DIVIDER_ONE_BASED BIT(0)
727 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
728 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
729 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
730 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
731 #define CLK_DIVIDER_READ_ONLY BIT(5)
732 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
733 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
734 #define CLK_DIVIDER_EVEN_INTEGERS BIT(8)
774 struct clk *clk_register_divider_table(struct device *dev, const char *name,
780 * clk_register_divider - register a divider clock with the clock framework
784 * @flags: framework-specific flags
785 * @reg: register address to adjust divider
788 * @clk_divider_flags: divider-specific flags for this clock
797 * clk_hw_register_divider - register a divider clock with the clock framework
801 * @flags: framework-specific flags
802 * @reg: register address to adjust divider
805 * @clk_divider_flags: divider-specific flags for this clock
814 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
818 * @parent_hw: pointer to parent clk
819 * @flags: framework-specific flags
820 * @reg: register address to adjust divider
823 * @clk_divider_flags: divider-specific flags for this clock
833 * clk_hw_register_divider_parent_data - register a divider clock with the clock
837 * @parent_data: parent clk data
838 * @flags: framework-specific flags
839 * @reg: register address to adjust divider
842 * @clk_divider_flags: divider-specific flags for this clock
852 * clk_hw_register_divider_table - register a table based divider clock with
857 * @flags: framework-specific flags
858 * @reg: register address to adjust divider
861 * @clk_divider_flags: divider-specific flags for this clock
862 * @table: array of divider/value pairs ending with a div set to 0
872 * clk_hw_register_divider_table_parent_hw - register a table based divider
876 * @parent_hw: pointer to parent clk
877 * @flags: framework-specific flags
878 * @reg: register address to adjust divider
881 * @clk_divider_flags: divider-specific flags for this clock
882 * @table: array of divider/value pairs ending with a div set to 0
893 * clk_hw_register_divider_table_parent_data - register a table based divider
897 * @parent_data: parent clk data
898 * @flags: framework-specific flags
899 * @reg: register address to adjust divider
902 * @clk_divider_flags: divider-specific flags for this clock
903 * @table: array of divider/value pairs ending with a div set to 0
915 * devm_clk_hw_register_divider - register a divider clock with the clock framework
919 * @flags: framework-specific flags
920 * @reg: register address to adjust divider
923 * @clk_divider_flags: divider-specific flags for this clock
932 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
935 * @parent_hw: pointer to parent clk
936 * @flags: framework-specific flags
937 * @reg: register address to adjust divider
940 * @clk_divider_flags: divider-specific flags for this clock
951 * devm_clk_hw_register_divider_table - register a table based divider clock
956 * @flags: framework-specific flags
957 * @reg: register address to adjust divider
960 * @clk_divider_flags: divider-specific flags for this clock
961 * @table: array of divider/value pairs ending with a div set to 0
972 void clk_unregister_divider(struct clk *clk);
976 * struct clk_mux - multiplexer clock
978 * @hw: handle between common and hardware-specific interfaces
981 * @shift: shift to multiplexer bit field
982 * @mask: mask of mutliplexer bit field
983 * @flags: hardware-specific flags
990 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
991 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
992 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
993 * register, and mask of mux bits are in higher 16-bit of this register.
994 * While setting the mux bits, higher 16-bit should also be updated to
996 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
998 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1000 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1016 #define CLK_MUX_INDEX_ONE BIT(0)
1017 #define CLK_MUX_INDEX_BIT BIT(1)
1018 #define CLK_MUX_HIWORD_MASK BIT(2)
1019 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
1020 #define CLK_MUX_ROUND_CLOSEST BIT(4)
1021 #define CLK_MUX_BIG_ENDIAN BIT(5)
1040 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1048 (flags), (reg), (shift), BIT((width)) - 1, \
1068 (shift), BIT((width)) - 1, (clk_mux_flags), \
1074 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1080 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1087 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1092 (shift), BIT((width)) - 1, (clk_mux_flags), \
1099 (shift), BIT((width)) - 1, \
1107 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1113 void clk_unregister_mux(struct clk *clk);
1119 * struct clk_fixed_factor - fixed multiplier and divider clock
1121 * @hw: handle between common and hardware-specific interfaces
1123 * @div: divider
1127 * Clock with a fixed multiplier and divider. The output frequency is the
1132 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1133 * parent clk accuracy.
1144 #define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0)
1149 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1152 void clk_unregister_fixed_factor(struct clk *clk);
1189 * struct clk_fractional_divider - adjustable fractional divider clock
1191 * @hw: handle between common and hardware-specific interfaces
1192 * @reg: register containing the divider
1193 * @mshift: shift to the numerator bit field
1194 * @mwidth: width of the numerator bit field
1195 * @nshift: shift to the denominator bit field
1196 * @nwidth: width of the denominator bit field
1197 * @approximation: clk driver's callback for calculating the divider clock
1200 * Clock with adjustable fractional divider affecting its output frequency.
1203 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1207 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1208 * used for the divider register. Setting this flag makes the register
1210 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1215 * caller's side the power-of-two capable prescaler exists.
1233 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1234 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1235 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1237 struct clk *clk_register_fractional_divider(struct device *dev,
1248 * struct clk_multiplier - adjustable multiplier clock
1250 * @hw: handle between common and hardware-specific interfaces
1252 * @shift: shift to the multiplier bit field
1253 * @width: width of the multiplier bit field
1260 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1265 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1267 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1282 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1283 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1284 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1289 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1291 * @hw: handle between common and hardware-specific interfaces
1292 * @mux_hw: handle between composite and hardware-specific mux clock
1293 * @rate_hw: handle between composite and hardware-specific rate clock
1294 * @gate_hw: handle between composite and hardware-specific gate clock
1314 struct clk *clk_register_composite(struct device *dev, const char *name,
1320 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1326 void clk_unregister_composite(struct clk *clk);
1349 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1350 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1356 void clk_unregister(struct clk *clk);
1361 const char *__clk_get_name(const struct clk *clk);
1364 struct clk_hw *__clk_get_hw(struct clk *clk);
1366 static inline struct clk_hw *__clk_get_hw(struct clk *clk) in __clk_get_hw() argument
1368 return (struct clk_hw *)clk; in __clk_get_hw()
1372 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1373 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1382 unsigned int __clk_get_enable_count(struct clk *clk);
1390 bool __clk_is_enabled(struct clk *clk);
1391 struct clk *__clk_lookup(const char *name);
1410 dst->clk = src->clk; in __clk_hw_set_clk()
1411 dst->core = src->core; in __clk_hw_set_clk()
1440 struct clk **clks;
1455 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
1467 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1572 * fixed factor clk declarations.
1598 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1611 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1615 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1626 struct clk *(*clk_src_get)(struct of_phandle_args *args, in of_clk_add_provider()
1648 static inline struct clk *of_clk_src_simple_get( in of_clk_src_simple_get()
1651 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1656 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1658 static inline struct clk *of_clk_src_onecell_get( in of_clk_src_onecell_get()
1661 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1666 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()