Lines Matching +full:rev +full:- +full:mii
1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
50 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
51 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
53 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
57 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
91 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
92 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
110 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
132 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
133 #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
134 #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
142 #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
193 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
194 #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
213 #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
227 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
228 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
229 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
242 #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
250 #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
282 /* Block 0x140 - 0x190 registers are chipset specific */
306 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
323 /* PMU registers (rev >= 20) */
453 /* PMU rev 15 */
470 /* ALP clock on pre-PMU chips */
472 /* HT clock for systems with PMU-enabled chipcommon */
475 /* PMU rev 5 (& 6) */
517 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
530 /* 43224 chip-specific ChipControl register bits */
577 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
581 u8 rev; /* PMU revision */ member
605 * de-reference that structure.
660 void __iomem *mii; member
665 bcma_read32((cc)->core, offset)
667 bcma_write32((cc)->core, offset, val)
678 bcma_read32((cc)->pmu.core, offset)
680 bcma_write32((cc)->pmu.core, offset, val)