Lines Matching +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
106 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
107 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
139 /* Start/busy bit in flashcontrol */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
248 #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
263 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
282 /* Block 0x140 - 0x190 registers are chipset specific */
435 #define BCMA_CC_PMU4716_MAINPLL_PLL0 12
447 #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
470 /* ALP clock on pre-PMU chips */
472 /* HT clock for systems with PMU-enabled chipcommon */
514 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
515 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
516 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
517 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
518 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
519 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
520 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
521 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout …
522 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
523 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
524 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
525 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
526 #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
527 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
528 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
530 /* 43224 chip-specific ChipControl register bits */
532 #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
533 #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
536 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
539 #define BCMA_CHIPCTL_5357_EXTPA BIT(14)
540 #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
541 #define BCMA_CHIPCTL_5357_NFLASH BIT(16)
542 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
543 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
545 #define BCMA_RES_4314_LPLDO_PU BIT(0)
546 #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
547 #define BCMA_RES_4314_PMU_BG_PU BIT(2)
548 #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
549 #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
550 #define BCMA_RES_4314_CLDO_PU BIT(5)
551 #define BCMA_RES_4314_LPLDO2_LVM BIT(6)
552 #define BCMA_RES_4314_WL_PMU_PU BIT(7)
553 #define BCMA_RES_4314_LNLDO_PU BIT(8)
554 #define BCMA_RES_4314_LDO3P3_PU BIT(9)
555 #define BCMA_RES_4314_OTP_PU BIT(10)
556 #define BCMA_RES_4314_XTAL_PU BIT(11)
557 #define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
558 #define BCMA_RES_4314_LQ_AVAIL BIT(13)
559 #define BCMA_RES_4314_LOGIC_RET BIT(14)
560 #define BCMA_RES_4314_MEM_SLEEP BIT(15)
561 #define BCMA_RES_4314_MACPHY_RET BIT(16)
562 #define BCMA_RES_4314_WL_CORE_READY BIT(17)
563 #define BCMA_RES_4314_ILP_REQ BIT(18)
564 #define BCMA_RES_4314_ALP_AVAIL BIT(19)
565 #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
566 #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
567 #define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
568 #define BCMA_RES_4314_RADIO_PU BIT(23)
569 #define BCMA_RES_4314_VCO_LDO_PU BIT(24)
570 #define BCMA_RES_4314_AFE_LDO_PU BIT(25)
571 #define BCMA_RES_4314_RX_LDO_PU BIT(26)
572 #define BCMA_RES_4314_TX_LDO_PU BIT(27)
573 #define BCMA_RES_4314_HT_AVAIL BIT(28)
574 #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
577 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
605 * de-reference that structure.
665 bcma_read32((cc)->core, offset)
667 bcma_write32((cc)->core, offset, val)
678 bcma_read32((cc)->pmu.core, offset)
680 bcma_write32((cc)->pmu.core, offset, val)