Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)
111 #define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11)
122 #define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
123 #define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1)
124 #define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2)
125 #define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3)
126 #define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4)
127 #define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5)
128 #define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6)
129 #define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7)
130 #define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8)
131 #define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9)
132 #define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10)
133 #define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11)
134 #define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12)
135 #define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13)
136 #define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14)
137 #define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15)
138 #define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16)
139 #define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17)
140 #define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18)
141 #define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
142 #define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20)
143 #define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21)
144 #define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22)
145 #define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23)
148 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)
149 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1)
150 #define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2)
151 #define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3)
152 #define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4)
153 #define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5)
154 #define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6)
155 #define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7)
156 #define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8)
157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9)
194 #define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10)
195 #define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11)
213 #define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10)
214 #define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11)
246 #define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)
247 #define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)
275 #define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10)
276 #define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11)
332 #define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10)
333 #define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11)
346 #define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10)
347 #define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11)
360 #define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10)
361 #define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11)
374 #define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10)
375 #define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11)